69 lines
2.7 KiB
C
69 lines
2.7 KiB
C
/*
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* Copyright (C) 2012 Altera Corporation <www.altera.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _SYSTEM_MANAGER_H_
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#define _SYSTEM_MANAGER_H_
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void socfpga_sysmgr_pinmux_init(unsigned long *sys_mgr_init_table, int num);
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/* address */
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#define CONFIG_SYSMGR_ROMCODEGRP_CTRL (CYCLONE5_SYSMGR_ADDRESS + 0xc0)
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/* FPGA interface group */
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#define SYSMGR_FPGAINTF_MODULE (CYCLONE5_SYSMGR_ADDRESS + 0x28)
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/* EMAC interface selection */
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#define CONFIG_SYSMGR_EMAC_CTRL (CYCLONE5_SYSMGR_ADDRESS + 0x60)
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#define ISWGRP_HANDOFF_AXIBRIDGE SYSMGR_ISWGRP_HANDOFF0
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#define ISWGRP_HANDOFF_L3REMAP SYSMGR_ISWGRP_HANDOFF1
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#define ISWGRP_HANDOFF_FPGAINTF SYSMGR_ISWGRP_HANDOFF2
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#define ISWGRP_HANDOFF_FPGA2SDR SYSMGR_ISWGRP_HANDOFF3
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/* pin mux */
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#define SYSMGR_PINMUXGRP (CYCLONE5_SYSMGR_ADDRESS + 0x400)
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#define SYSMGR_PINMUXGRP_NANDUSEFPGA (SYSMGR_PINMUXGRP + 0x2F0)
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#define SYSMGR_PINMUXGRP_EMAC1USEFPGA (SYSMGR_PINMUXGRP + 0x2F8)
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#define SYSMGR_PINMUXGRP_SDMMCUSEFPGA (SYSMGR_PINMUXGRP + 0x308)
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#define SYSMGR_PINMUXGRP_EMAC0USEFPGA (SYSMGR_PINMUXGRP + 0x314)
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#define SYSMGR_PINMUXGRP_SPIM1USEFPGA (SYSMGR_PINMUXGRP + 0x330)
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#define SYSMGR_PINMUXGRP_SPIM0USEFPGA (SYSMGR_PINMUXGRP + 0x338)
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/* bit fields */
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#define CONFIG_SYSMGR_PINMUXGRP_OFFSET (0x400)
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#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX (1<<0)
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#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO (1<<1)
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#define SYSMGR_ECC_OCRAM_EN (1<<0)
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#define SYSMGR_ECC_OCRAM_SERR (1<<3)
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#define SYSMGR_ECC_OCRAM_DERR (1<<4)
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#define SYSMGR_FPGAINTF_USEFPGA 0x1
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#define SYSMGR_FPGAINTF_SPIM0 (1<<0)
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#define SYSMGR_FPGAINTF_SPIM1 (1<<1)
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#define SYSMGR_FPGAINTF_EMAC0 (1<<2)
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#define SYSMGR_FPGAINTF_EMAC1 (1<<3)
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#define SYSMGR_FPGAINTF_NAND (1<<4)
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#define SYSMGR_FPGAINTF_SDMMC (1<<5)
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/* Enumeration: sysmgr::emacgrp::ctrl::physel::enum */
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#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0
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#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII 0x1
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#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII 0x2
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#define SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB 0
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#define SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB 2
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#define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK 0x00000003
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#endif /* _SYSTEM_MANAGER_H_ */
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