f937e19dc1
After separation and after all S3C macros are now present, change the driver to be more generic for future additions. The timer registers in the S3C24XX family are only 16 bit wide. But these registers can be read and written in a 32 bit manner. This is important to share code with more recent CPUs which comes with 32 bit registers. Signed-off-by: Juergen Beisert <jbe@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
115 lines
3 KiB
C
115 lines
3 KiB
C
/*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <config.h>
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#include <common.h>
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#include <init.h>
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#include <clock.h>
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#include <io.h>
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#include <mach/s3c-iomap.h>
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#include <mach/s3c-generic.h>
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#define S3C_TCFG0 (S3C_TIMER_BASE + 0x00)
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# define S3C_TCFG0_T4MASK 0xff00
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# define S3C_TCFG0_SET_PSCL234(x) ((x) << 8)
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# define S3C_TCFG0_GET_PSCL234(x) (((x) >> 8) & 0xff)
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#define S3C_TCFG1 (S3C_TIMER_BASE + 0x04)
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# define S3C_TCFG1_T4MASK 0xf0000
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# define S3C_TCFG1_SET_T4MUX(x) ((x) << 16)
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# define S3C_TCFG1_GET_T4MUX(x) (((x) >> 16) & 0xf)
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#define S3C_TCON (S3C_TIMER_BASE + 0x08)
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# define S3C_TCON_T4MASK (7 << 20)
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# define S3C_TCON_T4START (1 << 20)
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# define S3C_TCON_T4MANUALUPD (1 << 21)
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# define S3C_TCON_T4RELOAD (1 <<22)
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#define S3C_TCNTB4 (S3C_TIMER_BASE + 0x3c)
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#define S3C_TCNTO4 (S3C_TIMER_BASE + 0x40)
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#define TIMER_WIDTH 16
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#define TIMER_SHIFT 10
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#define PRE_MUX 3
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#define PRE_MUX_ADD 1
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static const uint32_t max = 0x0000ffff;
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static void s3c_init_t4_clk_source(void)
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{
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unsigned reg;
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reg = readl(S3C_TCON) & ~S3C_TCON_T4MASK; /* stop timer 4 */
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writel(reg, S3C_TCON);
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reg = readl(S3C_TCFG0) & ~S3C_TCFG0_T4MASK;
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reg |= S3C_TCFG0_SET_PSCL234(0); /* 0 means pre scaler is '256' */
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writel(reg, S3C_TCFG0);
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reg = readl(S3C_TCFG1) & ~S3C_TCFG1_T4MASK;
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reg |= S3C_TCFG1_SET_T4MUX(PRE_MUX); /* / 16 */
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writel(reg, S3C_TCFG1);
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}
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static unsigned s3c_get_t4_clk(void)
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{
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unsigned clk = s3c_get_pclk();
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unsigned pre = S3C_TCFG0_GET_PSCL234(readl(S3C_TCFG0)) + 1;
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unsigned div = S3C_TCFG1_GET_T4MUX(readl(S3C_TCFG1)) + PRE_MUX_ADD;
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return clk / pre / (1 << div);
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}
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static void s3c_timer_init(void)
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{
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unsigned tcon;
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tcon = readl(S3C_TCON) & ~S3C_TCON_T4MASK;
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writel(max, S3C_TCNTB4); /* reload value */
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/* force a manual counter update */
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writel(tcon | S3C_TCON_T4MANUALUPD, S3C_TCON);
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}
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static void s3c_timer_start(void)
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{
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unsigned tcon;
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tcon = readl(S3C_TCON) & ~S3C_TCON_T4MANUALUPD;
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tcon |= S3C_TCON_T4START | S3C_TCON_T4RELOAD;
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writel(tcon, S3C_TCON);
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}
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static uint64_t s3c_clocksource_read(void)
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{
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/* note: its a down counter */
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return max - readl(S3C_TCNTO4);
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}
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static struct clocksource cs = {
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.read = s3c_clocksource_read,
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.mask = CLOCKSOURCE_MASK(TIMER_WIDTH),
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.shift = TIMER_SHIFT,
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};
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static int s3c_clk_src_init(void)
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{
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/* select its clock source first */
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s3c_init_t4_clk_source();
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s3c_timer_init();
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s3c_timer_start();
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cs.mult = clocksource_hz2mult(s3c_get_t4_clk(), cs.shift);
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init_clock(&cs);
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return 0;
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}
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core_initcall(s3c_clk_src_init);
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