178 lines
5.2 KiB
C
178 lines
5.2 KiB
C
/*
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*
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* (c) 2011 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <common.h>
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#include <init.h>
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#include <mach/imx25-regs.h>
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#include <mach/esdctl.h>
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#include <io.h>
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#include <sizes.h>
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#include <mach/imx-nand.h>
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#include <mach/esdctl.h>
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#include <asm/barebox-arm.h>
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#include <asm/barebox-arm-head.h>
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#include <asm/system.h>
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#include <asm/sections.h>
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#include <asm-generic/memory_layout.h>
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#include <debug_ll.h>
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static inline void setup_uart(void)
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{
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void __iomem *uartbase = (void *)MX25_UART1_BASE_ADDR;
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void __iomem *iomuxbase = (void *)MX25_IOMUXC_BASE_ADDR;
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writel(0x0, iomuxbase + 0x174);
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writel(0x00000000, uartbase + 0x80);
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writel(0x00004027, uartbase + 0x84);
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writel(0x00000704, uartbase + 0x88);
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writel(0x00000a81, uartbase + 0x90);
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writel(0x0000002b, uartbase + 0x9c);
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writel(0x00013880, uartbase + 0xb0);
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writel(0x0000047f, uartbase + 0xa4);
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writel(0x0000a259, uartbase + 0xa8);
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writel(0x00000001, uartbase + 0x80);
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putc_ll('>');
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}
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static inline void __bare_init setup_sdram(uint32_t base, uint32_t esdctl,
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uint32_t esdcfg)
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{
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uint32_t esdctlreg = MX25_ESDCTL_BASE_ADDR + IMX_ESDCTL0;
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uint32_t esdcfgreg = MX25_ESDCTL_BASE_ADDR + IMX_ESDCFG0;
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if (base == 0x90000000) {
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esdctlreg += 8;
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esdcfgreg += 8;
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}
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esdctl |= ESDCTL0_SDE;
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writel(esdcfg, esdcfgreg);
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writel(esdctl | ESDCTL0_SMODE_PRECHARGE, esdctlreg);
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writel(0, base + 1024);
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writel(esdctl | ESDCTL0_SMODE_AUTO_REFRESH, esdctlreg);
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readb(base);
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readb(base);
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writel(esdctl | ESDCTL0_SMODE_LOAD_MODE, esdctlreg);
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writeb(0, base + 0x33);
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writel(esdctl, esdctlreg);
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}
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static void __bare_init karo_tx25_common_init(uint32_t fdt)
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{
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uint32_t r;
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arm_cpu_lowlevel_init();
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/* AIPS setup - Only setup MPROTx registers. The PACR default values are good.
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* Set all MPROTx to be non-bufferable, trusted for R/W,
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* not forced to user-mode.
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*/
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writel(0x77777777, 0x43f00000);
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writel(0x77777777, 0x43f00004);
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writel(0x77777777, 0x53f00000);
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writel(0x77777777, 0x53f00004);
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/* MAX (Multi-Layer AHB Crossbar Switch) setup
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* MPR - priority for MX25 is (SDHC2/SDMA)>USBOTG>RTIC>IAHB>DAHB
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*/
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writel(0x00043210, 0x43f04000);
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writel(0x00043210, 0x43f04100);
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writel(0x00043210, 0x43f04200);
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writel(0x00043210, 0x43f04300);
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writel(0x00043210, 0x43f04400);
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/* SGPCR - always park on last master */
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writel(0x10, 0x43f04010);
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writel(0x10, 0x43f04110);
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writel(0x10, 0x43f04210);
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writel(0x10, 0x43f04310);
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writel(0x10, 0x43f04410);
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/* MGPCR - restore default values */
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writel(0x0, 0x43f04800);
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writel(0x0, 0x43f04900);
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writel(0x0, 0x43f04a00);
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writel(0x0, 0x43f04b00);
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writel(0x0, 0x43f04c00);
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/* Configure M3IF registers
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* M3IF Control Register (M3IFCTL) for MX25
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* MRRP[0] = LCDC on priority list (1 << 0) = 0x00000001
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* MRRP[1] = MAX1 not on priority list (0 << 1) = 0x00000000
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* MRRP[2] = MAX0 not on priority list (0 << 2) = 0x00000000
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* MRRP[3] = USB HOST not on priority list (0 << 3) = 0x00000000
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* MRRP[4] = SDMA not on priority list (0 << 4) = 0x00000000
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* MRRP[5] = SD/ATA/FEC not on priority list (0 << 5) = 0x00000000
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* MRRP[6] = SCMFBC not on priority list (0 << 6) = 0x00000000
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* MRRP[7] = CSI not on priority list (0 << 7) = 0x00000000
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* ----------
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* 0x00000001
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*/
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writel(0x1, 0xb8003000);
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/* configure ARM clk */
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writel(0x20034000, MX25_CCM_BASE_ADDR + MX25_CCM_CCTL);
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/* enable all the clocks */
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writel(0x1fffffff, MX25_CCM_BASE_ADDR + MX25_CCM_CGCR0);
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writel(0xffffffff, MX25_CCM_BASE_ADDR + MX25_CCM_CGCR1);
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writel(0x000fdfff, MX25_CCM_BASE_ADDR + MX25_CCM_CGCR2);
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setup_uart();
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/* Skip SDRAM initialization if we run from RAM */
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r = get_pc();
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if (r > 0x80000000 && r < 0xa0000000)
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goto out;
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/* set to 3.3v SDRAM */
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writel(0x800, MX25_IOMUXC_BASE_ADDR + 0x454);
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writel(ESDMISC_RST, MX25_ESDCTL_BASE_ADDR + IMX_ESDMISC);
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while (!(readl(MX25_ESDCTL_BASE_ADDR + IMX_ESDMISC) & (1 << 31)));
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#define ESDCTLVAL (ESDCTL0_ROW13 | ESDCTL0_COL9 | ESDCTL0_DSIZ_15_0 | \
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ESDCTL0_REF4 | ESDCTL0_PWDT_PRECHARGE_PWDN | ESDCTL0_BL)
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#define ESDCFGVAL (ESDCFGx_tRP_3 | ESDCFGx_tMRD_2 | ESDCFGx_tRAS_6 | \
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ESDCFGx_tRRD_2 | ESDCFGx_tCAS_3 | ESDCFGx_tRCD_3 | \
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ESDCFGx_tRC_9)
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setup_sdram(0x80000000, ESDCTLVAL, ESDCFGVAL);
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setup_sdram(0x90000000, ESDCTLVAL, ESDCFGVAL);
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imx25_barebox_boot_nand_external(fdt);
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out:
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imx25_barebox_entry(fdt);
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}
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extern char __dtb_imx25_karo_tx25_start[];
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ENTRY_FUNCTION(start_imx25_karo_tx25, r0, r1, r2)
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{
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uint32_t fdt;
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arm_setup_stack(MX25_IRAM_BASE_ADDR + MX25_IRAM_SIZE - 8);
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fdt = (uint32_t)__dtb_imx25_karo_tx25_start - get_runtime_offset();
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karo_tx25_common_init(fdt);
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}
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