137 lines
2.7 KiB
C
137 lines
2.7 KiB
C
#include <common.h>
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#include <init.h>
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#include <asm/mmu.h>
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static unsigned long *ttb;
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void arm_create_section(unsigned long virt, unsigned long phys, int size_m,
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unsigned int flags)
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{
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int i;
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phys >>= 20;
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virt >>= 20;
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for (i = size_m; i > 0; i--, virt++, phys++)
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ttb[virt] = (phys << 20) | flags;
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asm volatile (
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"bl __mmu_cache_flush;"
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:
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:
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: "r0", "r1", "r2", "r3", "r6", "r10", "r12", "cc", "memory"
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);
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}
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/*
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* Prepare MMU for usage and create a flat mapping. Board
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* code is responsible to remap the SDRAM cached
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*/
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void mmu_init(void)
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{
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int i;
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ttb = xzalloc(0x8000);
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ttb = (void *)(((unsigned long)ttb + 0x4000) & ~0x3fff);
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/* Set the ttb register */
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asm volatile ("mcr p15,0,%0,c2,c0,0" : : "r"(ttb) /*:*/);
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/* Set the Domain Access Control Register */
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i = 0x3;
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asm volatile ("mcr p15,0,%0,c3,c0,0" : : "r"(i) /*:*/);
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/* create a flat mapping */
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arm_create_section(0, 0, 4096, PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | PMD_TYPE_SECT);
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}
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/*
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* enable the MMU. Should be called after mmu_init()
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*/
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void mmu_enable(void)
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{
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asm volatile (
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"bl __mmu_cache_on;"
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:
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:
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: "r0", "r1", "r2", "r3", "r6", "r10", "r12", "cc", "memory"
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);
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}
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struct outer_cache_fns outer_cache;
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/*
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* Clean and invalide caches, disable MMU
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*/
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void mmu_disable(void)
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{
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if (outer_cache.disable)
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outer_cache.disable();
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asm volatile (
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"bl __mmu_cache_flush;"
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"bl __mmu_cache_off;"
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:
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:
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: "r0", "r1", "r2", "r3", "r6", "r10", "r12", "cc", "memory"
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);
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}
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/*
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* For boards which need coherent memory for DMA. The idea
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* is simple: Setup a uncached section containing your SDRAM
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* and call setup_dma_coherent() with the offset between the
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* cached and the uncached section. dma_alloc_coherent() then
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* works using normal malloc but returns the corresponding
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* pointer in the uncached area.
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*/
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static unsigned long dma_coherent_offset;
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void setup_dma_coherent(unsigned long offset)
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{
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dma_coherent_offset = offset;
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}
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void *dma_alloc_coherent(size_t size)
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{
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return xmemalign(4096, size) + dma_coherent_offset;
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}
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unsigned long virt_to_phys(void *virt)
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{
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return (unsigned long)virt - dma_coherent_offset;
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}
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void *phys_to_virt(unsigned long phys)
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{
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return (void *)(phys + dma_coherent_offset);
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}
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void dma_free_coherent(void *mem)
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{
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free(mem - dma_coherent_offset);
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}
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void dma_clean_range(unsigned long start, unsigned long end)
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{
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if (outer_cache.clean_range)
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outer_cache.clean_range(start, end);
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__dma_clean_range(start, end);
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}
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void dma_flush_range(unsigned long start, unsigned long end)
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{
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if (outer_cache.flush_range)
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outer_cache.flush_range(start, end);
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__dma_flush_range(start, end);
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}
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void dma_inv_range(unsigned long start, unsigned long end)
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{
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if (outer_cache.inv_range)
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outer_cache.inv_range(start, end);
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__dma_inv_range(start, end);
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}
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