221 lines
6.4 KiB
C
221 lines
6.4 KiB
C
#include <common.h>
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#include <sizes.h>
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#include <io.h>
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#include <init.h>
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#include <asm/barebox-arm-head.h>
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#include <asm/barebox-arm.h>
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#include <mach/am33xx-silicon.h>
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#include <mach/am33xx-clock.h>
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#include <mach/generic.h>
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#include <mach/sdrc.h>
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#include <mach/sys_info.h>
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#include <mach/syslib.h>
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#include <mach/am33xx-mux.h>
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#include <mach/wdt.h>
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/* UART Defines */
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#define UART_SYSCFG_OFFSET (0x54)
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#define UART_SYSSTS_OFFSET (0x58)
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#define UART_RESET (0x1 << 1)
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#define UART_CLK_RUNNING_MASK 0x1
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#define UART_SMART_IDLE_EN (0x1 << 0x3)
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/* AM335X EMIF Register values */
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#define VTP_CTRL_READY (0x1 << 5)
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#define VTP_CTRL_ENABLE (0x1 << 6)
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#define VTP_CTRL_START_EN (0x1)
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#define CMD_FORCE 0x00 /* common #def */
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#define CMD_DELAY 0x00
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#define EMIF_READ_LATENCY 0x06
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#define EMIF_SDCFG 0x61C04832 /* CL 5, CWL 5 */
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#define EMIF_SDREF 0x0000093B
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#define EMIF_TIM1 0x0668A39B
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#define EMIF_TIM2 0x26337FDA
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#define EMIF_TIM3 0x501F830F
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#define DLL_LOCK_DIFF 0x0
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#define PHY_WR_DATA 0xC1
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#define RD_DQS 0x3B
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#define WR_DQS 0x85
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#define PHY_FIFO_WE 0x100
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#define INVERT_CLKOUT 0x1
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#define PHY_RANK0_DELAY 0x01
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#define DDR_IOCTRL_VALUE 0x18B
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#define CTRL_SLAVE_RATIO 0x40
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#define PHY_LVL_MODE 0x1
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#define DDR_ZQ_CFG 0x50074BE4
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static void Cmd_Macro_Config(void)
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{
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writel(CTRL_SLAVE_RATIO, AM33XX_CMD0_CTRL_SLAVE_RATIO_0);
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writel(CMD_FORCE, AM33XX_CMD0_CTRL_SLAVE_FORCE_0);
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writel(CMD_DELAY, AM33XX_CMD0_CTRL_SLAVE_DELAY_0);
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writel(DLL_LOCK_DIFF, AM33XX_CMD0_DLL_LOCK_DIFF_0);
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writel(INVERT_CLKOUT, AM33XX_CMD0_INVERT_CLKOUT_0);
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writel(CTRL_SLAVE_RATIO, AM33XX_CMD1_CTRL_SLAVE_RATIO_0);
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writel(CMD_FORCE, AM33XX_CMD1_CTRL_SLAVE_FORCE_0);
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writel(CMD_DELAY, AM33XX_CMD1_CTRL_SLAVE_DELAY_0);
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writel(DLL_LOCK_DIFF, AM33XX_CMD1_DLL_LOCK_DIFF_0);
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writel(INVERT_CLKOUT, AM33XX_CMD1_INVERT_CLKOUT_0);
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writel(CTRL_SLAVE_RATIO, AM33XX_CMD2_CTRL_SLAVE_RATIO_0);
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writel(CMD_FORCE, AM33XX_CMD2_CTRL_SLAVE_FORCE_0);
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writel(CMD_DELAY, AM33XX_CMD2_CTRL_SLAVE_DELAY_0);
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writel(DLL_LOCK_DIFF, AM33XX_CMD2_DLL_LOCK_DIFF_0);
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writel(INVERT_CLKOUT, AM33XX_CMD2_INVERT_CLKOUT_0);
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}
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static void config_vtp(void)
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{
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writel(readl(AM33XX_VTP0_CTRL_REG) | VTP_CTRL_ENABLE,
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AM33XX_VTP0_CTRL_REG);
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writel(readl(AM33XX_VTP0_CTRL_REG) & (~VTP_CTRL_START_EN),
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AM33XX_VTP0_CTRL_REG);
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writel(readl(AM33XX_VTP0_CTRL_REG) | VTP_CTRL_START_EN,
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AM33XX_VTP0_CTRL_REG);
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/* Poll for READY */
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while ((readl(AM33XX_VTP0_CTRL_REG) &
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VTP_CTRL_READY) != VTP_CTRL_READY);
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}
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static void phy_config_data(void)
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{
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writel(RD_DQS, AM33XX_DATA0_RD_DQS_SLAVE_RATIO_0);
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writel(WR_DQS, AM33XX_DATA0_WR_DQS_SLAVE_RATIO_0);
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writel(PHY_FIFO_WE, AM33XX_DATA0_FIFO_WE_SLAVE_RATIO_0);
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writel(PHY_WR_DATA, AM33XX_DATA0_WR_DATA_SLAVE_RATIO_0);
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writel(RD_DQS, AM33XX_DATA1_RD_DQS_SLAVE_RATIO_0);
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writel(WR_DQS, AM33XX_DATA1_WR_DQS_SLAVE_RATIO_0);
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writel(PHY_FIFO_WE, AM33XX_DATA1_FIFO_WE_SLAVE_RATIO_0);
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writel(PHY_WR_DATA, AM33XX_DATA1_WR_DATA_SLAVE_RATIO_0);
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}
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static void config_emif(void)
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{
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/*Program EMIF0 CFG Registers*/
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writel(EMIF_READ_LATENCY, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_1));
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writel(EMIF_READ_LATENCY,
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AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_1_SHADOW));
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writel(EMIF_READ_LATENCY, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_2));
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writel(EMIF_TIM1, AM33XX_EMIF4_0_REG(SDRAM_TIM_1));
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writel(EMIF_TIM1, AM33XX_EMIF4_0_REG(SDRAM_TIM_1_SHADOW));
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writel(EMIF_TIM2, AM33XX_EMIF4_0_REG(SDRAM_TIM_2));
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writel(EMIF_TIM2, AM33XX_EMIF4_0_REG(SDRAM_TIM_2_SHADOW));
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writel(EMIF_TIM3, AM33XX_EMIF4_0_REG(SDRAM_TIM_3));
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writel(EMIF_TIM3, AM33XX_EMIF4_0_REG(SDRAM_TIM_3_SHADOW));
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writel(EMIF_SDREF, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL));
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writel(EMIF_SDREF, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL_SHADOW));
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writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG));
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writel(DDR_ZQ_CFG, AM33XX_EMIF4_0_REG(ZQ_CONFIG));
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while ((readl(AM33XX_EMIF4_0_REG(SDRAM_STATUS)) & 0x4) != 0x4);
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}
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static void pcm051_config_ddr(void)
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{
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enable_ddr_clocks();
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config_vtp();
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/* init mode */
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writel(PHY_LVL_MODE, AM33XX_DATA0_WRLVL_INIT_MODE_0);
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writel(PHY_LVL_MODE, AM33XX_DATA0_GATELVL_INIT_MODE_0);
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writel(PHY_LVL_MODE, AM33XX_DATA1_WRLVL_INIT_MODE_0);
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writel(PHY_LVL_MODE, AM33XX_DATA1_GATELVL_INIT_MODE_0);
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Cmd_Macro_Config();
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phy_config_data();
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writel(PHY_RANK0_DELAY, AM33XX_DATA0_RANK0_DELAYS_0);
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writel(PHY_RANK0_DELAY, AM33XX_DATA1_RANK0_DELAYS_0);
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writel(DDR_IOCTRL_VALUE, AM33XX_DDR_CMD0_IOCTRL);
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writel(DDR_IOCTRL_VALUE, AM33XX_DDR_CMD1_IOCTRL);
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writel(DDR_IOCTRL_VALUE, AM33XX_DDR_CMD2_IOCTRL);
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writel(DDR_IOCTRL_VALUE, AM33XX_DDR_DATA0_IOCTRL);
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writel(DDR_IOCTRL_VALUE, AM33XX_DDR_DATA1_IOCTRL);
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writel(readl(AM33XX_DDR_IO_CTRL) &
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0xefffffff, AM33XX_DDR_IO_CTRL);
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writel(readl(AM33XX_DDR_CKE_CTRL) |
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0x00000001, AM33XX_DDR_CKE_CTRL);
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config_emif();
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}
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/*
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* early system init of muxing and clocks.
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*/
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void pcm051_sram_init(void)
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{
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u32 regVal, uart_base;
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/* Setup the PLLs and the clocks for the peripherals */
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pll_init(MPUPLL_M_600);
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pcm051_config_ddr();
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/* UART softreset */
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am33xx_enable_uart0_pin_mux();
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uart_base = AM33XX_UART0_BASE;
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regVal = readl(uart_base + UART_SYSCFG_OFFSET);
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regVal |= UART_RESET;
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writel(regVal, (uart_base + UART_SYSCFG_OFFSET));
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while ((readl(uart_base + UART_SYSSTS_OFFSET) &
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UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK);
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/* Disable smart idle */
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regVal = readl((uart_base + UART_SYSCFG_OFFSET));
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regVal |= UART_SMART_IDLE_EN;
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writel(regVal, (uart_base + UART_SYSCFG_OFFSET));
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}
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/**
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* @brief The basic entry point for board initialization.
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*
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* This is called as part of machine init (after arch init).
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* This is again called with stack in SRAM, so not too many
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* constructs possible here.
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*
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* @return void
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*/
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static int pcm051_board_init(void)
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{
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int in_sdram = running_in_sdram();
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/* WDT1 is already running when the bootloader gets control
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* Disable it to avoid "random" resets
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*/
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writel(WDT_DISABLE_CODE1, AM33XX_WDT_REG(WSPR));
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while (readl(AM33XX_WDT_REG(WWPS)) != 0x0);
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writel(WDT_DISABLE_CODE2, AM33XX_WDT_REG(WSPR));
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while (readl(AM33XX_WDT_REG(WWPS)) != 0x0);
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/* Dont reconfigure SDRAM while running in SDRAM! */
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if (!in_sdram)
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pcm051_sram_init();
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return 0;
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}
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void __naked __bare_init barebox_arm_reset_vector(uint32_t *data)
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{
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omap_save_bootinfo();
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arm_cpu_lowlevel_init();
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pcm051_board_init();
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barebox_arm_entry(0x80000000, SZ_512M, 0);
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}
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