744 lines
20 KiB
C
744 lines
20 KiB
C
/*
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* Address map functions for Marvell EBU SoCs (Kirkwood, Armada
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* 370/XP, Dove, Orion5x and MV78xx0)
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*
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* Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
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*
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* based on mbus driver from Linux
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* (C) Copyright 2008 Marvell Semiconductor
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*
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* The Marvell EBU SoCs have a configurable physical address space:
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* the physical address at which certain devices (PCIe, NOR, NAND,
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* etc.) sit can be configured. The configuration takes place through
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* two sets of registers:
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*
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* - One to configure the access of the CPU to the devices. Depending
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* on the families, there are between 8 and 20 configurable windows,
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* each can be use to create a physical memory window that maps to a
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* specific device. Devices are identified by a tuple (target,
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* attribute).
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*
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* - One to configure the access to the CPU to the SDRAM. There are
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* either 2 (for Dove) or 4 (for other families) windows to map the
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* SDRAM into the physical address space.
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*
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* This driver:
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*
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* - Reads out the SDRAM address decoding windows at initialization
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* time, and fills the mbus_dram_info structure with these
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* informations. The exported function mv_mbus_dram_info() allow
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* device drivers to get those informations related to the SDRAM
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* address decoding windows. This is because devices also have their
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* own windows (configured through registers that are part of each
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* device register space), and therefore the drivers for Marvell
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* devices have to configure those device -> SDRAM windows to ensure
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* that DMA works properly.
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*
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* - Provides an API for platform code or device drivers to
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* dynamically add or remove address decoding windows for the CPU ->
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* device accesses. This API is mvebu_mbus_add_window_by_id(),
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* mvebu_mbus_add_window_remap_by_id() and
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* mvebu_mbus_del_window().
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*
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* - Provides a debugfs interface in /sys/kernel/debug/mvebu-mbus/ to
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* see the list of CPU -> SDRAM windows and their configuration
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* (file 'sdram') and the list of CPU -> devices windows and their
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* configuration (file 'devices').
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*/
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#include <common.h>
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#include <init.h>
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#include <io.h>
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#include <of.h>
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#include <of_address.h>
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#include <linux/mbus.h>
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/* DDR target is the same on all platforms */
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#define TARGET_DDR 0
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/* CPU Address Decode Windows registers */
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#define WIN_CTRL_OFF 0x0000
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#define WIN_CTRL_ENABLE BIT(0)
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#define WIN_CTRL_TGT_MASK 0xf0
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#define WIN_CTRL_TGT_SHIFT 4
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#define WIN_CTRL_ATTR_MASK 0xff00
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#define WIN_CTRL_ATTR_SHIFT 8
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#define WIN_CTRL_SIZE_MASK 0xffff0000
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#define WIN_CTRL_SIZE_SHIFT 16
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#define WIN_BASE_OFF 0x0004
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#define WIN_BASE_LOW 0xffff0000
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#define WIN_BASE_HIGH 0xf
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#define WIN_REMAP_LO_OFF 0x0008
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#define WIN_REMAP_LOW 0xffff0000
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#define WIN_REMAP_HI_OFF 0x000c
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#define ATTR_HW_COHERENCY (0x1 << 4)
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#define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3))
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#define DDR_BASE_CS_HIGH_MASK 0xf
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#define DDR_BASE_CS_LOW_MASK 0xff000000
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#define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3))
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#define DDR_SIZE_ENABLED BIT(0)
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#define DDR_SIZE_CS_MASK 0x1c
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#define DDR_SIZE_CS_SHIFT 2
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#define DDR_SIZE_MASK 0xff000000
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#define DOVE_DDR_BASE_CS_OFF(n) ((n) << 4)
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struct mvebu_mbus_state;
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struct mvebu_mbus_soc_data {
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unsigned int num_wins;
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unsigned int num_remappable_wins;
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unsigned int (*win_cfg_offset)(const int win);
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void (*setup_cpu_target)(struct mvebu_mbus_state *s);
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};
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struct mvebu_mbus_state {
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struct device_d *dev;
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void __iomem *mbuswins_base;
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void __iomem *sdramwins_base;
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struct dentry *debugfs_root;
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struct dentry *debugfs_sdram;
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struct dentry *debugfs_devs;
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struct resource pcie_mem_aperture;
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struct resource pcie_io_aperture;
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const struct mvebu_mbus_soc_data *soc;
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int hw_io_coherency;
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};
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static struct mvebu_mbus_state mbus_state;
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static struct mbus_dram_target_info mbus_dram_info;
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/*
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* Functions to manipulate the address decoding windows
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*/
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static void mvebu_mbus_read_window(struct mvebu_mbus_state *mbus,
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int win, int *enabled, u64 *base,
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u32 *size, u8 *target, u8 *attr,
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u64 *remap)
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{
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void __iomem *addr = mbus->mbuswins_base +
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mbus->soc->win_cfg_offset(win);
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u32 basereg = readl(addr + WIN_BASE_OFF);
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u32 ctrlreg = readl(addr + WIN_CTRL_OFF);
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if (!(ctrlreg & WIN_CTRL_ENABLE)) {
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*enabled = 0;
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return;
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}
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*enabled = 1;
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*base = ((u64)basereg & WIN_BASE_HIGH) << 32;
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*base |= (basereg & WIN_BASE_LOW);
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*size = (ctrlreg | ~WIN_CTRL_SIZE_MASK) + 1;
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if (target)
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*target = (ctrlreg & WIN_CTRL_TGT_MASK) >> WIN_CTRL_TGT_SHIFT;
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if (attr)
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*attr = (ctrlreg & WIN_CTRL_ATTR_MASK) >> WIN_CTRL_ATTR_SHIFT;
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if (remap) {
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if (win < mbus->soc->num_remappable_wins) {
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u32 remap_low = readl(addr + WIN_REMAP_LO_OFF);
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u32 remap_hi = readl(addr + WIN_REMAP_HI_OFF);
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*remap = ((u64)remap_hi << 32) | remap_low;
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} else
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*remap = 0;
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}
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}
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static void mvebu_mbus_disable_window(struct mvebu_mbus_state *mbus,
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int win)
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{
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void __iomem *addr;
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addr = mbus->mbuswins_base + mbus->soc->win_cfg_offset(win);
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writel(0, addr + WIN_BASE_OFF);
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writel(0, addr + WIN_CTRL_OFF);
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if (win < mbus->soc->num_remappable_wins) {
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writel(0, addr + WIN_REMAP_LO_OFF);
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writel(0, addr + WIN_REMAP_HI_OFF);
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}
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}
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/* Checks whether the given window number is available */
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static int mvebu_mbus_window_is_free(struct mvebu_mbus_state *mbus,
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const int win)
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{
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void __iomem *addr = mbus->mbuswins_base +
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mbus->soc->win_cfg_offset(win);
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u32 ctrl = readl(addr + WIN_CTRL_OFF);
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return !(ctrl & WIN_CTRL_ENABLE);
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}
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/*
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* Checks whether the given (base, base+size) area doesn't overlap an
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* existing region
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*/
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static int mvebu_mbus_window_conflicts(struct mvebu_mbus_state *mbus,
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phys_addr_t base, size_t size,
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u8 target, u8 attr)
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{
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u64 end = (u64)base + size;
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int win;
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for (win = 0; win < mbus->soc->num_wins; win++) {
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u64 wbase, wend;
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u32 wsize;
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u8 wtarget, wattr;
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int enabled;
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mvebu_mbus_read_window(mbus, win,
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&enabled, &wbase, &wsize,
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&wtarget, &wattr, NULL);
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if (!enabled)
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continue;
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wend = wbase + wsize;
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/*
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* Check if the current window overlaps with the
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* proposed physical range
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*/
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if ((u64)base < wend && end > wbase)
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return 0;
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/*
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* Check if target/attribute conflicts
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*/
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if (target == wtarget && attr == wattr)
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return 0;
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}
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return 1;
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}
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static int mvebu_mbus_find_window(struct mvebu_mbus_state *mbus,
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phys_addr_t base, size_t size)
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{
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int win;
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for (win = 0; win < mbus->soc->num_wins; win++) {
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u64 wbase;
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u32 wsize;
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int enabled;
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mvebu_mbus_read_window(mbus, win,
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&enabled, &wbase, &wsize,
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NULL, NULL, NULL);
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if (!enabled)
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continue;
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if (base == wbase && size == wsize)
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return win;
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}
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return -ENODEV;
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}
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static int mvebu_mbus_setup_window(struct mvebu_mbus_state *mbus,
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int win, phys_addr_t base, size_t size,
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phys_addr_t remap, u8 target,
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u8 attr)
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{
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void __iomem *addr = mbus->mbuswins_base +
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mbus->soc->win_cfg_offset(win);
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u32 ctrl, remap_addr;
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ctrl = ((size - 1) & WIN_CTRL_SIZE_MASK) |
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(attr << WIN_CTRL_ATTR_SHIFT) |
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(target << WIN_CTRL_TGT_SHIFT) |
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WIN_CTRL_ENABLE;
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writel(base & WIN_BASE_LOW, addr + WIN_BASE_OFF);
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writel(ctrl, addr + WIN_CTRL_OFF);
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if (win < mbus->soc->num_remappable_wins) {
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if (remap == MVEBU_MBUS_NO_REMAP)
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remap_addr = base;
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else
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remap_addr = remap;
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writel(remap_addr & WIN_REMAP_LOW, addr + WIN_REMAP_LO_OFF);
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writel(0, addr + WIN_REMAP_HI_OFF);
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}
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return 0;
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}
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static int mvebu_mbus_alloc_window(struct mvebu_mbus_state *mbus,
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phys_addr_t base, size_t size,
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phys_addr_t remap, u8 target,
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u8 attr)
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{
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int win;
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if (remap == MVEBU_MBUS_NO_REMAP) {
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for (win = mbus->soc->num_remappable_wins;
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win < mbus->soc->num_wins; win++)
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if (mvebu_mbus_window_is_free(mbus, win))
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return mvebu_mbus_setup_window(mbus, win, base,
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size, remap,
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target, attr);
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}
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for (win = 0; win < mbus->soc->num_wins; win++)
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if (mvebu_mbus_window_is_free(mbus, win))
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return mvebu_mbus_setup_window(mbus, win, base, size,
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remap, target, attr);
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return -ENOMEM;
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}
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/*
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* SoC-specific functions and definitions
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*/
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static unsigned int armada_370_xp_mbus_win_offset(int win)
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{
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/* The register layout is a bit annoying and the below code
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* tries to cope with it.
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* - At offset 0x0, there are the registers for the first 8
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* windows, with 4 registers of 32 bits per window (ctrl,
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* base, remap low, remap high)
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* - Then at offset 0x80, there is a hole of 0x10 bytes for
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* the internal registers base address and internal units
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* sync barrier register.
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* - Then at offset 0x90, there the registers for 12
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* windows, with only 2 registers of 32 bits per window
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* (ctrl, base).
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*/
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if (win < 8)
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return win << 4;
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else
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return 0x90 + ((win - 8) << 3);
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}
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static unsigned int orion5x_mbus_win_offset(int win)
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{
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return win << 4;
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}
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static unsigned int mv78xx0_mbus_win_offset(int win)
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{
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if (win < 8)
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return win << 4;
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else
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return 0x900 + ((win - 8) << 4);
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}
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static void mvebu_mbus_default_setup_cpu_target(struct mvebu_mbus_state *mbus)
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{
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int i;
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int cs;
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mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
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for (i = 0, cs = 0; i < 4; i++) {
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u32 base = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i));
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u32 size = readl(mbus->sdramwins_base + DDR_SIZE_CS_OFF(i));
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/*
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* We only take care of entries for which the chip
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* select is enabled, and that don't have high base
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* address bits set (devices can only access the first
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* 32 bits of the memory).
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*/
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if ((size & DDR_SIZE_ENABLED) &&
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!(base & DDR_BASE_CS_HIGH_MASK)) {
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struct mbus_dram_window *w;
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w = &mbus_dram_info.cs[cs++];
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w->cs_index = i;
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w->mbus_attr = 0xf & ~(1 << i);
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if (mbus->hw_io_coherency)
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w->mbus_attr |= ATTR_HW_COHERENCY;
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w->base = base & DDR_BASE_CS_LOW_MASK;
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w->size = (size | ~DDR_SIZE_MASK) + 1;
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}
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}
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mbus_dram_info.num_cs = cs;
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}
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static void mvebu_mbus_dove_setup_cpu_target(struct mvebu_mbus_state *mbus)
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{
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int i;
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int cs;
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mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
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for (i = 0, cs = 0; i < 2; i++) {
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u32 map = readl(mbus->sdramwins_base + DOVE_DDR_BASE_CS_OFF(i));
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/*
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* Chip select enabled?
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*/
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if (map & 1) {
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struct mbus_dram_window *w;
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w = &mbus_dram_info.cs[cs++];
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w->cs_index = i;
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w->mbus_attr = 0; /* CS address decoding done inside */
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/* the DDR controller, no need to */
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/* provide attributes */
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w->base = map & 0xff800000;
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w->size = 0x100000 << (((map & 0x000f0000) >> 16) - 4);
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}
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}
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mbus_dram_info.num_cs = cs;
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}
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static const struct mvebu_mbus_soc_data
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armada_370_xp_mbus_data __maybe_unused = {
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.num_wins = 20,
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.num_remappable_wins = 8,
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.win_cfg_offset = armada_370_xp_mbus_win_offset,
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.setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
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};
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static const struct mvebu_mbus_soc_data
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dove_mbus_data __maybe_unused = {
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.num_wins = 8,
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.num_remappable_wins = 4,
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.win_cfg_offset = orion5x_mbus_win_offset,
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.setup_cpu_target = mvebu_mbus_dove_setup_cpu_target,
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};
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static const struct mvebu_mbus_soc_data
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kirkwood_mbus_data __maybe_unused = {
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.num_wins = 8,
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.num_remappable_wins = 4,
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.win_cfg_offset = orion5x_mbus_win_offset,
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.setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
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};
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/*
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* Some variants of Orion5x have 4 remappable windows, some other have
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* only two of them.
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*/
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static const struct mvebu_mbus_soc_data
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orion5x_4win_mbus_data __maybe_unused = {
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.num_wins = 8,
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.num_remappable_wins = 4,
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.win_cfg_offset = orion5x_mbus_win_offset,
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.setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
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};
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static const struct mvebu_mbus_soc_data
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orion5x_2win_mbus_data__maybe_unused = {
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.num_wins = 8,
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.num_remappable_wins = 2,
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.win_cfg_offset = orion5x_mbus_win_offset,
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.setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
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};
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static const struct mvebu_mbus_soc_data
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mv78xx0_mbus_data __maybe_unused = {
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.num_wins = 14,
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.num_remappable_wins = 8,
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.win_cfg_offset = mv78xx0_mbus_win_offset,
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.setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
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};
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static struct of_device_id mvebu_mbus_dt_ids[] = {
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#if defined(CONFIG_ARCH_ARMADA_370) || defined(CONFIG_ARCH_ARMADA_XP)
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{ .compatible = "marvell,armada370-mbus",
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.data = (u32)&armada_370_xp_mbus_data, },
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{ .compatible = "marvell,armadaxp-mbus",
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.data = (u32)&armada_370_xp_mbus_data, },
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#endif
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#if defined(CONFIG_ARCH_DOVE)
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{ .compatible = "marvell,dove-mbus",
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.data = (u32)&dove_mbus_data, },
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#endif
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#if defined(CONFIG_ARCH_KIRKWOOD)
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{ .compatible = "marvell,kirkwood-mbus",
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.data = (u32)&kirkwood_mbus_data, },
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#endif
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#if defined(CONFIG_ARCH_ORION5X)
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{ .compatible = "marvell,orion5x-88f5281-mbus",
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.data = (u32)&orion5x_4win_mbus_data, },
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{ .compatible = "marvell,orion5x-88f5182-mbus",
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.data = (u32)&orion5x_2win_mbus_data, },
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{ .compatible = "marvell,orion5x-88f5181-mbus",
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.data = (u32)&orion5x_2win_mbus_data, },
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{ .compatible = "marvell,orion5x-88f6183-mbus",
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.data = (u32)&orion5x_4win_mbus_data, },
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#endif
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#if defined(CONFIG_ARCH_MV78XX0)
|
|
{ .compatible = "marvell,mv78xx0-mbus",
|
|
.data = (u32)&mv78xx0_mbus_data, },
|
|
#endif
|
|
{ },
|
|
};
|
|
|
|
/*
|
|
* Public API of the driver
|
|
*/
|
|
const struct mbus_dram_target_info *mvebu_mbus_dram_info(void)
|
|
{
|
|
return &mbus_dram_info;
|
|
}
|
|
|
|
int mvebu_mbus_add_window_remap_by_id(unsigned int target,
|
|
unsigned int attribute,
|
|
phys_addr_t base, size_t size,
|
|
phys_addr_t remap)
|
|
{
|
|
struct mvebu_mbus_state *s = &mbus_state;
|
|
|
|
if (!mvebu_mbus_window_conflicts(s, base, size, target, attribute)) {
|
|
dev_err(s->dev, "cannot add window '%x:%x', conflicts with another window\n",
|
|
target, attribute);
|
|
return -EINVAL;
|
|
}
|
|
|
|
return mvebu_mbus_alloc_window(s, base, size, remap, target, attribute);
|
|
}
|
|
|
|
int mvebu_mbus_add_window_by_id(unsigned int target, unsigned int attribute,
|
|
phys_addr_t base, size_t size)
|
|
{
|
|
return mvebu_mbus_add_window_remap_by_id(target, attribute, base,
|
|
size, MVEBU_MBUS_NO_REMAP);
|
|
}
|
|
|
|
int mvebu_mbus_del_window(phys_addr_t base, size_t size)
|
|
{
|
|
int win;
|
|
|
|
win = mvebu_mbus_find_window(&mbus_state, base, size);
|
|
if (win < 0)
|
|
return win;
|
|
|
|
mvebu_mbus_disable_window(&mbus_state, win);
|
|
return 0;
|
|
}
|
|
|
|
void mvebu_mbus_get_pcie_mem_aperture(struct resource *res)
|
|
{
|
|
if (!res)
|
|
return;
|
|
*res = mbus_state.pcie_mem_aperture;
|
|
}
|
|
|
|
void mvebu_mbus_get_pcie_io_aperture(struct resource *res)
|
|
{
|
|
if (!res)
|
|
return;
|
|
*res = mbus_state.pcie_io_aperture;
|
|
}
|
|
|
|
/*
|
|
* The window IDs in the ranges DT property have the following format:
|
|
* - bits 28 to 31: MBus custom field
|
|
* - bits 24 to 27: window target ID
|
|
* - bits 16 to 23: window attribute ID
|
|
* - bits 0 to 15: unused
|
|
*/
|
|
#define CUSTOM(id) (((id) & 0xF0000000) >> 24)
|
|
#define TARGET(id) (((id) & 0x0F000000) >> 24)
|
|
#define ATTR(id) (((id) & 0x00FF0000) >> 16)
|
|
|
|
static int mbus_dt_setup_win(struct mvebu_mbus_state *mbus,
|
|
u32 base, u32 size, u8 target, u8 attr)
|
|
{
|
|
if (!mvebu_mbus_window_conflicts(mbus, base, size, target, attr)) {
|
|
dev_err(mbus->dev, "cannot add window '%04x:%04x', conflicts with another window\n",
|
|
target, attr);
|
|
return -EBUSY;
|
|
}
|
|
|
|
if (mvebu_mbus_alloc_window(mbus, base, size, MVEBU_MBUS_NO_REMAP,
|
|
target, attr)) {
|
|
dev_err(mbus->dev, "cannot add window '%04x:%04x', too many windows\n",
|
|
target, attr);
|
|
return -ENOMEM;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static int mbus_parse_ranges(struct mvebu_mbus_state *mbus, int *addr_cells,
|
|
int *c_addr_cells, int *c_size_cells,
|
|
int *cell_count, const __be32 **ranges_start,
|
|
const __be32 **ranges_end)
|
|
{
|
|
struct device_node *node = mbus->dev->device_node;
|
|
const __be32 *prop;
|
|
int ranges_len, tuple_len;
|
|
|
|
/* Allow a node with no 'ranges' property */
|
|
*ranges_start = of_get_property(node, "ranges", &ranges_len);
|
|
if (*ranges_start == NULL) {
|
|
*addr_cells = *c_addr_cells = *c_size_cells = *cell_count = 0;
|
|
*ranges_start = *ranges_end = NULL;
|
|
return 0;
|
|
}
|
|
*ranges_end = *ranges_start + ranges_len / sizeof(__be32);
|
|
|
|
*addr_cells = of_n_addr_cells(node);
|
|
|
|
prop = of_get_property(node, "#address-cells", NULL);
|
|
*c_addr_cells = be32_to_cpup(prop);
|
|
|
|
prop = of_get_property(node, "#size-cells", NULL);
|
|
*c_size_cells = be32_to_cpup(prop);
|
|
|
|
*cell_count = *addr_cells + *c_addr_cells + *c_size_cells;
|
|
tuple_len = (*cell_count) * sizeof(__be32);
|
|
|
|
if (ranges_len % tuple_len) {
|
|
dev_warn(mbus->dev, "malformed ranges entry '%s'\n",
|
|
node->name);
|
|
return -EINVAL;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static int mbus_dt_setup(struct mvebu_mbus_state *mbus)
|
|
{
|
|
int addr_cells, c_addr_cells, c_size_cells;
|
|
int i, ret, cell_count;
|
|
const __be32 *r, *ranges_start, *ranges_end;
|
|
|
|
ret = mbus_parse_ranges(mbus, &addr_cells, &c_addr_cells,
|
|
&c_size_cells, &cell_count,
|
|
&ranges_start, &ranges_end);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
for (i = 0, r = ranges_start; r < ranges_end; r += cell_count, i++) {
|
|
u32 windowid, base, size;
|
|
u8 target, attr;
|
|
|
|
/*
|
|
* An entry with a non-zero custom field do not
|
|
* correspond to a static window, so skip it.
|
|
*/
|
|
windowid = of_read_number(r, 1);
|
|
if (CUSTOM(windowid))
|
|
continue;
|
|
|
|
target = TARGET(windowid);
|
|
attr = ATTR(windowid);
|
|
|
|
base = of_read_number(r + c_addr_cells, addr_cells);
|
|
size = of_read_number(r + c_addr_cells + addr_cells,
|
|
c_size_cells);
|
|
ret = mbus_dt_setup_win(mbus, base, size, target, attr);
|
|
if (ret < 0)
|
|
return ret;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static void mvebu_mbus_get_pcie_resources(struct device_node *np,
|
|
struct resource *mem, struct resource *io)
|
|
{
|
|
u32 reg[2];
|
|
int ret;
|
|
|
|
/*
|
|
* These are optional, so we make sure that resource_size(x) will
|
|
* return 0.
|
|
*/
|
|
memset(mem, 0, sizeof(struct resource));
|
|
mem->end = -1;
|
|
memset(io, 0, sizeof(struct resource));
|
|
io->end = -1;
|
|
|
|
ret = of_property_read_u32_array(np, "pcie-mem-aperture",
|
|
reg, ARRAY_SIZE(reg));
|
|
if (!ret) {
|
|
mem->start = reg[0];
|
|
mem->end = mem->start + reg[1];
|
|
mem->flags = IORESOURCE_MEM;
|
|
}
|
|
|
|
ret = of_property_read_u32_array(np, "pcie-io-aperture",
|
|
reg, ARRAY_SIZE(reg));
|
|
if (!ret) {
|
|
io->start = reg[0];
|
|
io->end = io->start + reg[1];
|
|
io->flags = IORESOURCE_IO;
|
|
}
|
|
}
|
|
|
|
static int mvebu_mbus_probe(struct device_d *dev)
|
|
{
|
|
struct device_node *np, *controller;
|
|
const struct of_device_id *match;
|
|
const __be32 *prop;
|
|
int win;
|
|
|
|
mbus_state.dev = dev;
|
|
|
|
np = of_find_matching_node_and_match(NULL, mvebu_mbus_dt_ids, &match);
|
|
if (!np) {
|
|
dev_err(dev, "could not find a matching SoC family\n");
|
|
return -ENODEV;
|
|
}
|
|
mbus_state.soc = (struct mvebu_mbus_soc_data *)match->data;
|
|
|
|
prop = of_get_property(np, "controller", NULL);
|
|
if (!prop) {
|
|
dev_err(dev, "required 'controller' property missing\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
controller = of_find_node_by_phandle(be32_to_cpup(prop));
|
|
if (!controller) {
|
|
dev_err(dev, "could not find an 'mbus-controller' node\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
mbus_state.mbuswins_base = of_iomap(controller, 0);
|
|
if (!mbus_state.mbuswins_base) {
|
|
dev_err(dev, "cannot get MBUS register address\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
mbus_state.sdramwins_base = of_iomap(controller, 1);
|
|
if (!mbus_state.sdramwins_base) {
|
|
dev_err(dev, "cannot get SDRAM register address\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
/* Get optional pcie-{mem,io}-aperture properties */
|
|
mvebu_mbus_get_pcie_resources(np, &mbus_state.pcie_mem_aperture,
|
|
&mbus_state.pcie_io_aperture);
|
|
|
|
if (of_find_compatible_node(NULL, NULL, "marvell,coherency-fabric"))
|
|
mbus_state.hw_io_coherency = 1;
|
|
|
|
for (win = 0; win < mbus_state.soc->num_wins; win++)
|
|
mvebu_mbus_disable_window(&mbus_state, win);
|
|
|
|
mbus_state.soc->setup_cpu_target(&mbus_state);
|
|
|
|
/* Setup statically declared windows in the DT */
|
|
return mbus_dt_setup(&mbus_state);
|
|
}
|
|
|
|
static struct driver_d mvebu_mbus_driver = {
|
|
.probe = mvebu_mbus_probe,
|
|
.name = "mvebu-mbus",
|
|
.of_compatible = DRV_OF_COMPAT(mvebu_mbus_dt_ids),
|
|
};
|
|
|
|
static int mvebu_mbus_init(void)
|
|
{
|
|
return platform_driver_register(&mvebu_mbus_driver);
|
|
}
|
|
postcore_initcall(mvebu_mbus_init);
|