12c101bcfd
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
184 lines
4.3 KiB
C
184 lines
4.3 KiB
C
#include <common.h>
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#include <init.h>
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#include <asm/io.h>
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#include <asm/mmu.h>
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#define CACHE_LINE_SIZE 32
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static void __iomem *l2x0_base;
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#define L2X0_CACHE_ID 0x000
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#define L2X0_CACHE_TYPE 0x004
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#define L2X0_CTRL 0x100
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#define L2X0_AUX_CTRL 0x104
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#define L2X0_TAG_LATENCY_CTRL 0x108
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#define L2X0_DATA_LATENCY_CTRL 0x10C
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#define L2X0_EVENT_CNT_CTRL 0x200
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#define L2X0_EVENT_CNT1_CFG 0x204
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#define L2X0_EVENT_CNT0_CFG 0x208
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#define L2X0_EVENT_CNT1_VAL 0x20C
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#define L2X0_EVENT_CNT0_VAL 0x210
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#define L2X0_INTR_MASK 0x214
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#define L2X0_MASKED_INTR_STAT 0x218
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#define L2X0_RAW_INTR_STAT 0x21C
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#define L2X0_INTR_CLEAR 0x220
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#define L2X0_CACHE_SYNC 0x730
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#define L2X0_INV_LINE_PA 0x770
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#define L2X0_INV_WAY 0x77C
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#define L2X0_CLEAN_LINE_PA 0x7B0
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#define L2X0_CLEAN_LINE_IDX 0x7B8
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#define L2X0_CLEAN_WAY 0x7BC
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#define L2X0_CLEAN_INV_LINE_PA 0x7F0
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#define L2X0_CLEAN_INV_LINE_IDX 0x7F8
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#define L2X0_CLEAN_INV_WAY 0x7FC
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#define L2X0_LOCKDOWN_WAY_D 0x900
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#define L2X0_LOCKDOWN_WAY_I 0x904
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#define L2X0_TEST_OPERATION 0xF00
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#define L2X0_LINE_DATA 0xF10
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#define L2X0_LINE_TAG 0xF30
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#define L2X0_DEBUG_CTRL 0xF40
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static inline void cache_wait(void __iomem *reg, unsigned long mask)
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{
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/* wait for the operation to complete */
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while (readl(reg) & mask)
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;
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}
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static inline void cache_sync(void)
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{
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void __iomem *base = l2x0_base;
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writel(0, base + L2X0_CACHE_SYNC);
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cache_wait(base + L2X0_CACHE_SYNC, 1);
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}
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static inline void l2x0_clean_line(unsigned long addr)
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{
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void __iomem *base = l2x0_base;
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cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
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writel(addr, base + L2X0_CLEAN_LINE_PA);
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}
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static inline void l2x0_inv_line(unsigned long addr)
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{
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void __iomem *base = l2x0_base;
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cache_wait(base + L2X0_INV_LINE_PA, 1);
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writel(addr, base + L2X0_INV_LINE_PA);
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}
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static inline void l2x0_flush_line(unsigned long addr)
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{
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void __iomem *base = l2x0_base;
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/* Clean by PA followed by Invalidate by PA */
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cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
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writel(addr, base + L2X0_CLEAN_LINE_PA);
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cache_wait(base + L2X0_INV_LINE_PA, 1);
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writel(addr, base + L2X0_INV_LINE_PA);
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}
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static inline void l2x0_inv_all(void)
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{
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/* invalidate all ways */
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writel(0xff, l2x0_base + L2X0_INV_WAY);
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cache_wait(l2x0_base + L2X0_INV_WAY, 0xff);
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cache_sync();
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}
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static void l2x0_inv_range(unsigned long start, unsigned long end)
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{
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if (start & (CACHE_LINE_SIZE - 1)) {
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start &= ~(CACHE_LINE_SIZE - 1);
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l2x0_flush_line(start);
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start += CACHE_LINE_SIZE;
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}
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if (end & (CACHE_LINE_SIZE - 1)) {
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end &= ~(CACHE_LINE_SIZE - 1);
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l2x0_flush_line(end);
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}
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while (start < end) {
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unsigned long blk_end = start + min(end - start, 4096UL);
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while (start < blk_end) {
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l2x0_inv_line(start);
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start += CACHE_LINE_SIZE;
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}
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}
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cache_wait(l2x0_base + L2X0_INV_LINE_PA, 1);
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cache_sync();
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}
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static void l2x0_clean_range(unsigned long start, unsigned long end)
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{
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void __iomem *base = l2x0_base;
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start &= ~(CACHE_LINE_SIZE - 1);
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while (start < end) {
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unsigned long blk_end = start + min(end - start, 4096UL);
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while (start < blk_end) {
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l2x0_clean_line(start);
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start += CACHE_LINE_SIZE;
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}
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}
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cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
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cache_sync();
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}
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static void l2x0_flush_range(unsigned long start, unsigned long end)
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{
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start &= ~(CACHE_LINE_SIZE - 1);
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while (start < end) {
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unsigned long blk_end = start + min(end - start, 4096UL);
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while (start < blk_end) {
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l2x0_flush_line(start);
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start += CACHE_LINE_SIZE;
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}
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}
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cache_wait(l2x0_base + L2X0_CLEAN_INV_LINE_PA, 1);
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cache_sync();
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}
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static void l2x0_disable(void)
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{
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writel(0xff, l2x0_base + L2X0_CLEAN_INV_WAY);
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while (readl(l2x0_base + L2X0_CLEAN_INV_WAY));
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writel(0, l2x0_base + L2X0_CTRL);
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}
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void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask)
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{
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__u32 aux;
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l2x0_base = base;
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/*
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* Check if l2x0 controller is already enabled.
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* If you are booting from non-secure mode
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* accessing the below registers will fault.
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*/
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if (!(readl(l2x0_base + L2X0_CTRL) & 1)) {
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/* l2x0 controller is disabled */
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aux = readl(l2x0_base + L2X0_AUX_CTRL);
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aux &= aux_mask;
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aux |= aux_val;
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writel(aux, l2x0_base + L2X0_AUX_CTRL);
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l2x0_inv_all();
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/* enable L2X0 */
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writel(1, l2x0_base + L2X0_CTRL);
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}
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outer_cache.inv_range = l2x0_inv_range;
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outer_cache.clean_range = l2x0_clean_range;
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outer_cache.flush_range = l2x0_flush_range;
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outer_cache.disable = l2x0_disable;
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}
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