163 lines
3.4 KiB
ArmAsm
163 lines
3.4 KiB
ArmAsm
/*
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* Copyright (C) 2010 Jaccon Bastiaansen <jaccon.bastiaansen@gmail.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <asm-generic/memory_layout.h>
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#include <mach/imx-regs.h>
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.section ".text_bare_init","ax"
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.globl board_init_lowlevel
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board_init_lowlevel:
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/* Save lr, because it is overwritten by the calls to mem_delay. */
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mov r10, lr
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/*
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* Initialize the AHB-Lite IP Interface (AIPI) module (to enable access to
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* on chip peripherals) as described in section 7.2 of rev3 of the i.MX21
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* reference manual.
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*/
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ldr r0, =AIPI1_PSR0
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ldr r1, =0x00040304
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str r1, [r0]
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ldr r0, =AIPI1_PSR1
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ldr r1, =0xfffbfcfb
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str r1, [r0]
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ldr r0, =AIPI2_PSR0
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ldr r1, =0x3ffc0000
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str r1, [r0]
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ldr r0, =AIPI2_PSR1
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ldr r1, =0xffffffff
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str r1, [r0]
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/*
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* Configure CPU core clock (266MHz), peripheral clock (133MHz) and enable
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* the clock to peripherals.
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*/
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ldr r0, =CSCR
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ldr r1, =0x17180607
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str r1, [r0]
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ldr r0, =PCCR1
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ldr r1, =0x0e000000
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str r1, [r0]
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/*
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* SDRAM and SDRAM controller configuration
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*/
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/*
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* CSD1 not required, because the MX21ADS board only contains 64Mbyte.
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* CS3 can therefore be made available.
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*/
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ldr r0, =FMCR
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ldr r1, =0xffffffc9
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str r1, [r0]
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/* Skip SDRAM initialization if we run from RAM */
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cmp pc, #0xc0000000
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bls 1f
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cmp pc, #0xc8000000
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bhi 1f
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mov pc, r10
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1:
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/* Precharge */
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ldr r0, =SDCTL0
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ldr r1, =0x92120300
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str r1, [r0]
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ldr r2, =0xc0200000
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ldr r1, [r2]
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bl mem_delay
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/* Auto refresh */
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ldr r1, =0xa2120300
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str r1, [r0]
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ldr r2, =0xc0000000
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ldr r1, [r2]
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ldr r1, [r2]
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ldr r1, [r2]
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ldr r1, [r2]
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ldr r1, [r2]
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ldr r1, [r2]
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ldr r1, [r2]
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ldr r1, [r2]
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/* Set mode register */
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ldr r1, =0xB2120300
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str r1, [r0]
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ldr r1, =0xC0119800
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ldr r2, [r1]
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bl mem_delay
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/* Back to Normal Mode */
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ldr r1, =0x8212F339
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str r1, [r0]
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/* Set NFC_CLK to 24MHz */
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ldr r0, =PCDR0
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ldr r1, =0x6419a007
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str r1, [r0]
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#ifdef CONFIG_NAND_IMX_BOOT
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ldr sp, =STACK_BASE + STACK_SIZE - 12 /* Setup a temporary stack in SDRAM */
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ldr r0, =IMX_NFC_BASE /* start of NFC SRAM */
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ldr r2, =IMX_NFC_BASE + 0x800 /* end of NFC SRAM */
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/* skip NAND boot if not running from NFC space */
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cmp pc, r0
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bls ret
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cmp pc, r2
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bhi ret
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/* Move ourselves out of NFC SRAM */
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ldr r1, =_text
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copy_loop:
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ldmia r0!, {r3-r9} /* copy from source address [r0] */
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stmia r1!, {r3-r9} /* copy to target address [r1] */
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cmp r0, r2 /* until source end address [r2] */
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ble copy_loop
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ldr pc, =1f /* Jump to SDRAM */
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1:
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b nand_boot /* Load barebox from NAND Flash */
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/* SRAM to SDRAM */
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#endif /* CONFIG_NAND_IMX_BOOT */
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ret:
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mov pc, r10
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/*
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* spin for a while. we need to wait at least 200 usecs.
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*/
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mem_delay:
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mov r4, #0x4000
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spin: subs r4, r4, #1
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bne spin
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mov pc, lr
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