7cc98fbb61
This commit adds basic mmu support, ie:
- DMA cache handling is not supported
- Remapping memory region also
The current mmu setting is:
- 4KB granularity
- 3 level lookup (skipping L0)
- 33 bits per VA
This is based on coreboot and u-boot mmu configuration.
Signed-off-by: Raphael Poggi <poggi.raph@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
69 lines
1.7 KiB
C
69 lines
1.7 KiB
C
#ifndef __ARM_MMU_H
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#define __ARM_MMU_H
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#ifdef CONFIG_CPU_64v8
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#define TCR_FLAGS (TCR_TG0_4K | \
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TCR_SHARED_OUTER | \
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TCR_SHARED_INNER | \
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TCR_IRGN_WBWA | \
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TCR_ORGN_WBWA | \
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TCR_T0SZ(BITS_PER_VA))
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#ifndef __ASSEMBLY__
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static inline void set_ttbr_tcr_mair(int el, uint64_t table, uint64_t tcr, uint64_t attr)
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{
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asm volatile("dsb sy");
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if (el == 1) {
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asm volatile("msr ttbr0_el1, %0" : : "r" (table) : "memory");
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asm volatile("msr tcr_el1, %0" : : "r" (tcr) : "memory");
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asm volatile("msr mair_el1, %0" : : "r" (attr) : "memory");
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} else if (el == 2) {
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asm volatile("msr ttbr0_el2, %0" : : "r" (table) : "memory");
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asm volatile("msr tcr_el2, %0" : : "r" (tcr) : "memory");
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asm volatile("msr mair_el2, %0" : : "r" (attr) : "memory");
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} else if (el == 3) {
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asm volatile("msr ttbr0_el3, %0" : : "r" (table) : "memory");
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asm volatile("msr tcr_el3, %0" : : "r" (tcr) : "memory");
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asm volatile("msr mair_el3, %0" : : "r" (attr) : "memory");
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} else {
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hang();
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}
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asm volatile("isb");
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}
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static inline uint64_t get_ttbr(int el)
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{
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uint64_t val;
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if (el == 1) {
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asm volatile("mrs %0, ttbr0_el1" : "=r" (val));
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} else if (el == 2) {
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asm volatile("mrs %0, ttbr0_el2" : "=r" (val));
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} else if (el == 3) {
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asm volatile("mrs %0, ttbr0_el3" : "=r" (val));
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} else {
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hang();
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}
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return val;
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}
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void mmu_early_enable(uint64_t membase, uint64_t memsize, uint64_t _ttb);
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#endif
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#endif /* CONFIG_CPU_64v8 */
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#ifdef CONFIG_MMU
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void __mmu_cache_on(void);
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void __mmu_cache_off(void);
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void __mmu_cache_flush(void);
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#else
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static inline void __mmu_cache_on(void) {}
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static inline void __mmu_cache_off(void) {}
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static inline void __mmu_cache_flush(void) {}
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#endif
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#endif /* __ARM_MMU_H */
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