Refactoring of CLPS711X CLK driver code to be compatible with the current kernel. This change a bit makes easy of initializing devices using CLKs. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
95 lines
2.5 KiB
C
95 lines
2.5 KiB
C
/*
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* Copyright (C) 2012-2016 Alexander Shiyan <shc_work@mail.ru>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*/
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#include <common.h>
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#include <init.h>
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#include <asm/io.h>
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#include <linux/clk.h>
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#include <linux/clkdev.h>
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#include <linux/sizes.h>
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#include <dt-bindings/clock/clps711x-clock.h>
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#include <mach/clps711x.h>
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#define CLPS711X_OSC_FREQ 3686400
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#define CLPS711X_EXT_FREQ 13000000
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static struct clk *clks[CLPS711X_CLK_MAX];
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static struct clk_div_table tdiv_tbl[] = {
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{ .val = 0, .div = 256, },
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{ .val = 1, .div = 1, },
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};
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static __init int clps711x_clk_init(void)
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{
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unsigned int f_cpu, f_bus, f_uart, f_timer_ref, pll;
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u32 tmp;
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tmp = readl(PLLR) >> 24;
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if (tmp)
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pll = (CLPS711X_OSC_FREQ * tmp) / 2;
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else
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pll = 73728000; /* Default value for old CPUs */
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tmp = readl(SYSFLG2);
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if (tmp & SYSFLG2_CKMODE) {
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f_cpu = CLPS711X_EXT_FREQ;
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f_bus = CLPS711X_EXT_FREQ;
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} else {
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f_cpu = pll;
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if (f_cpu >= 36864000)
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f_bus = f_cpu / 2;
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else
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f_bus = 36864000 / 2;
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}
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f_uart = f_bus / 10;
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if (tmp & SYSFLG2_CKMODE) {
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tmp = readw(SYSCON2);
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if (tmp & SYSCON2_OSTB)
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f_timer_ref = DIV_ROUND_CLOSEST(CLPS711X_EXT_FREQ, 26);
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else
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f_timer_ref = DIV_ROUND_CLOSEST(CLPS711X_EXT_FREQ, 24);
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} else
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f_timer_ref = DIV_ROUND_CLOSEST(f_cpu, 144);
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/* Turn timers in free running mode */
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tmp = readl(SYSCON1);
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tmp &= ~(SYSCON1_TC1M | SYSCON1_TC2M);
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writel(tmp, SYSCON1);
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clks[CLPS711X_CLK_DUMMY] = clk_fixed("dummy", 0);
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clks[CLPS711X_CLK_CPU] = clk_fixed("cpu", f_cpu);
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clks[CLPS711X_CLK_BUS] = clk_fixed("bus", f_bus);
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clks[CLPS711X_CLK_UART] = clk_fixed("uart", f_uart);
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clks[CLPS711X_CLK_TIMERREF] = clk_fixed("timer_ref", f_timer_ref);
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clks[CLPS711X_CLK_TIMER1] = clk_divider_table("timer1", "timer_ref",
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IOMEM(SYSCON1), 5, 1, tdiv_tbl, ARRAY_SIZE(tdiv_tbl));
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clks[CLPS711X_CLK_TIMER2] = clk_divider_table("timer2", "timer_ref",
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IOMEM(SYSCON1), 7, 1, tdiv_tbl, ARRAY_SIZE(tdiv_tbl));
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clkdev_add_physbase(clks[CLPS711X_CLK_UART], UARTDR1, NULL);
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clkdev_add_physbase(clks[CLPS711X_CLK_UART], UARTDR2, NULL);
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clkdev_add_physbase(clks[CLPS711X_CLK_TIMER2], TC2D, NULL);
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return 0;
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}
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postcore_initcall(clps711x_clk_init);
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static __init int clps711x_core_init(void)
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{
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add_generic_device("clps711x-cs", DEVICE_ID_SINGLE, NULL,
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TC2D, SZ_2, IORESOURCE_MEM, NULL);
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return 0;
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}
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coredevice_initcall(clps711x_core_init);
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