Signed-off-by: Wadim Egorov <w.egorov@phytec.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
524 lines
12 KiB
C
524 lines
12 KiB
C
/*
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* (C) Copyright 2012 Teresa Gámez, Phytec Messtechnik GmbH
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* (C) Copyright 2012-2013 Jan Luebbe <j.luebbe@pengutronix.de>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <common.h>
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#include <bootsource.h>
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#include <init.h>
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#include <io.h>
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#include <net.h>
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#include <restart.h>
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#include <asm/barebox-arm.h>
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#include <mach/am33xx-silicon.h>
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#include <mach/am33xx-clock.h>
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#include <mach/generic.h>
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#include <mach/sys_info.h>
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#include <mach/am33xx-generic.h>
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#include <mach/gpmc.h>
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#include <reset_source.h>
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static void __noreturn am33xx_restart_soc(struct restart_handler *rst)
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{
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writel(AM33XX_PRM_RSTCTRL_RESET, AM33XX_PRM_RSTCTRL);
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hang();
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}
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/**
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* @brief Extract the AM33xx ES revision
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*
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* The significance of the CPU revision depends upon the cpu type.
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* Latest known revision is considered default.
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*
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* This function is called before barebox_arm_entry(), so avoid switch
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* statements.
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*
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* @return silicon version
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*/
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u32 am33xx_get_cpu_rev(void)
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{
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u32 version = (readl(AM33XX_IDCODE_REG) >> 28) & 0xF;
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if (version == 0)
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return AM335X_ES1_0;
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else if (version == 1)
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return AM335X_ES2_0;
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else
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return AM335X_ES2_1;
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}
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/**
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* @brief Get the upper address of current execution
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*
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* we can use this to figure out if we are running in SRAM /
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* XIP Flash or in SDRAM
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*
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* @return base address
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*/
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static u32 get_base(void)
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{
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u32 val;
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__asm__ __volatile__("mov %0, pc \n":"=r"(val)::"memory");
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val &= 0xF0000000;
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val >>= 28;
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return val;
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}
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/**
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* @brief Are we running in Flash XIP?
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*
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* If the base is in GPMC address space, we probably are!
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*
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* @return 1 if we are running in XIP mode, else return 0
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*/
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u32 am33xx_running_in_flash(void)
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{
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if (get_base() < 4)
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return 1; /* in flash */
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return 0; /* running in SRAM or SDRAM */
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}
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/**
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* @brief Are we running in OMAP internal SRAM?
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*
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* If in SRAM address, then yes!
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*
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* @return 1 if we are running in SRAM, else return 0
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*/
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u32 am33xx_running_in_sram(void)
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{
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if (get_base() == 4)
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return 1; /* in SRAM */
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return 0; /* running in FLASH or SDRAM */
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}
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/**
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* @brief Are we running in SDRAM?
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*
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* if we are not in GPMC nor in SRAM address space,
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* we are in SDRAM execution area
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*
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* @return 1 if we are running from SDRAM, else return 0
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*/
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u32 am33xx_running_in_sdram(void)
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{
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if (get_base() > 4)
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return 1; /* in sdram */
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return 0; /* running in SRAM or FLASH */
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}
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static int am33xx_bootsource(void)
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{
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enum bootsource src;
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int instance = 0;
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uint32_t *am33xx_bootinfo = (void *)AM33XX_SRAM_SCRATCH_SPACE;
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switch (am33xx_bootinfo[2] & 0xFF) {
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case 0x05:
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src = BOOTSOURCE_NAND;
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break;
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case 0x08:
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src = BOOTSOURCE_MMC;
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instance = 0;
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break;
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case 0x09:
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src = BOOTSOURCE_MMC;
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instance = 1;
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break;
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case 0x0b:
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src = BOOTSOURCE_SPI;
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break;
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case 0x41:
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src = BOOTSOURCE_SERIAL;
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break;
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case 0x44:
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src = BOOTSOURCE_USB;
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break;
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case 0x46:
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src = BOOTSOURCE_NET;
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break;
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default:
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src = BOOTSOURCE_UNKNOWN;
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}
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bootsource_set(src);
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bootsource_set_instance(instance);
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return 0;
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}
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static void am33xx_detect_reset_reason(void)
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{
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uint32_t val = 0;
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val = readl(AM33XX_PRM_RSTST);
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/* clear AM33XX_PRM_RSTST - must be cleared by software
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* (warm reset insensitive) */
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writel(val, AM33XX_PRM_RSTST);
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switch (val) {
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case (1 << 9):
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reset_source_set(RESET_JTAG);
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break;
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case (1 << 5):
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reset_source_set(RESET_EXT);
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break;
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case (1 << 4):
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case (1 << 3):
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reset_source_set(RESET_WDG);
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break;
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case (1 << 1):
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reset_source_set(RESET_RST);
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break;
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case (1 << 0):
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reset_source_set(RESET_POR);
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break;
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default:
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reset_source_set(RESET_UKWN);
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break;
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}
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}
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int am33xx_register_ethaddr(int eth_id, int mac_id)
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{
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void __iomem *mac_id_low = (void *)AM33XX_MAC_ID0_LO + mac_id * 8;
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void __iomem *mac_id_high = (void *)AM33XX_MAC_ID0_HI + mac_id * 8;
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uint8_t mac_addr[6];
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uint32_t mac_hi, mac_lo;
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mac_lo = readl(mac_id_low);
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mac_hi = readl(mac_id_high);
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mac_addr[0] = mac_hi & 0xff;
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mac_addr[1] = (mac_hi & 0xff00) >> 8;
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mac_addr[2] = (mac_hi & 0xff0000) >> 16;
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mac_addr[3] = (mac_hi & 0xff000000) >> 24;
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mac_addr[4] = mac_lo & 0xff;
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mac_addr[5] = (mac_lo & 0xff00) >> 8;
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if (is_valid_ether_addr(mac_addr)) {
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eth_register_ethaddr(eth_id, mac_addr);
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return 0;
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}
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return -ENODEV;
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}
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/* GPMC timing for AM33XX nand device */
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const struct gpmc_config am33xx_nand_cfg = {
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.cfg = {
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0x00000800, /* CONF1 */
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0x001e1e00, /* CONF2 */
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0x001e1e00, /* CONF3 */
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0x16051807, /* CONF4 */
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0x00151e1e, /* CONF5 */
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0x16000f80, /* CONF6 */
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},
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.base = 0x08000000,
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.size = GPMC_SIZE_16M,
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};
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static int am33xx_gpio_init(void)
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{
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add_generic_device("omap-gpio", 0, NULL, AM33XX_GPIO0_BASE,
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0xf00, IORESOURCE_MEM, NULL);
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add_generic_device("omap-gpio", 1, NULL, AM33XX_GPIO1_BASE,
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0xf00, IORESOURCE_MEM, NULL);
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add_generic_device("omap-gpio", 2, NULL, AM33XX_GPIO2_BASE,
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0xf00, IORESOURCE_MEM, NULL);
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add_generic_device("omap-gpio", 3, NULL, AM33XX_GPIO3_BASE,
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0xf00, IORESOURCE_MEM, NULL);
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return 0;
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}
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int am33xx_init(void)
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{
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omap_gpmc_base = (void *)AM33XX_GPMC_BASE;
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restart_handler_register_fn(am33xx_restart_soc);
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am33xx_enable_per_clocks();
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if (IS_ENABLED(CONFIG_RESET_SOURCE))
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am33xx_detect_reset_reason();
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return am33xx_bootsource();
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}
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int am33xx_devices_init(void)
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{
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return am33xx_gpio_init();
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}
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/* UART Defines */
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#define UART_SYSCFG_OFFSET 0x54
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#define UART_SYSSTS_OFFSET 0x58
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#define UART_CLK_RUNNING_MASK 0x1
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#define UART_RESET (0x1 << 1)
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#define UART_SMART_IDLE_EN (0x1 << 0x3)
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void am33xx_uart_soft_reset(void __iomem *uart_base)
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{
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int reg;
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reg = readl(uart_base + UART_SYSCFG_OFFSET);
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reg |= UART_RESET;
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writel(reg, (uart_base + UART_SYSCFG_OFFSET));
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while ((readl(uart_base + UART_SYSSTS_OFFSET) &
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UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
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;
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/* Disable smart idle */
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reg = readl((uart_base + UART_SYSCFG_OFFSET));
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reg |= UART_SMART_IDLE_EN;
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writel(reg, (uart_base + UART_SYSCFG_OFFSET));
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}
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#define VTP_CTRL_READY (0x1 << 5)
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#define VTP_CTRL_ENABLE (0x1 << 6)
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#define VTP_CTRL_START_EN (0x1)
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void am33xx_config_vtp(void)
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{
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uint32_t val;
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val = readl(AM33XX_VTP0_CTRL_REG);
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val |= VTP_CTRL_ENABLE;
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writel(val, AM33XX_VTP0_CTRL_REG);
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val = readl(AM33XX_VTP0_CTRL_REG);
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val &= ~VTP_CTRL_START_EN;
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writel(val, AM33XX_VTP0_CTRL_REG);
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val = readl(AM33XX_VTP0_CTRL_REG);
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val |= VTP_CTRL_START_EN;
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writel(val, AM33XX_VTP0_CTRL_REG);
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/* Poll for READY */
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while ((readl(AM33XX_VTP0_CTRL_REG) &
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VTP_CTRL_READY) != VTP_CTRL_READY)
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;
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}
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void am33xx_ddr_phydata_cmd_macro(const struct am33xx_cmd_control *cmd_ctrl)
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{
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writel(cmd_ctrl->slave_ratio0, AM33XX_CMD0_CTRL_SLAVE_RATIO_0);
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writel(cmd_ctrl->dll_lock_diff0, AM33XX_CMD0_DLL_LOCK_DIFF_0);
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writel(cmd_ctrl->invert_clkout0, AM33XX_CMD0_INVERT_CLKOUT_0);
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writel(cmd_ctrl->slave_ratio1, AM33XX_CMD1_CTRL_SLAVE_RATIO_0);
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writel(cmd_ctrl->dll_lock_diff1, AM33XX_CMD1_DLL_LOCK_DIFF_0);
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writel(cmd_ctrl->invert_clkout1, AM33XX_CMD1_INVERT_CLKOUT_0);
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writel(cmd_ctrl->slave_ratio2, AM33XX_CMD2_CTRL_SLAVE_RATIO_0);
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writel(cmd_ctrl->dll_lock_diff2, AM33XX_CMD2_DLL_LOCK_DIFF_0);
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writel(cmd_ctrl->invert_clkout2, AM33XX_CMD2_INVERT_CLKOUT_0);
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}
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#define CM_EMIF_SDRAM_CONFIG (AM33XX_CTRL_BASE + 0x110)
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void am33xx_config_sdram(const struct am33xx_emif_regs *regs)
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{
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writel(regs->emif_read_latency, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_1));
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writel(regs->emif_read_latency, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_1_SHADOW));
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writel(regs->emif_read_latency, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_2));
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writel(regs->emif_tim1, AM33XX_EMIF4_0_REG(SDRAM_TIM_1));
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writel(regs->emif_tim1, AM33XX_EMIF4_0_REG(SDRAM_TIM_1_SHADOW));
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writel(regs->emif_tim2, AM33XX_EMIF4_0_REG(SDRAM_TIM_2));
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writel(regs->emif_tim2, AM33XX_EMIF4_0_REG(SDRAM_TIM_2_SHADOW));
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writel(regs->emif_tim3, AM33XX_EMIF4_0_REG(SDRAM_TIM_3));
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writel(regs->emif_tim3, AM33XX_EMIF4_0_REG(SDRAM_TIM_3_SHADOW));
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if (regs->zq_config) {
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/*
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* A value of 0x2800 for the REF CTRL will give us
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* about 570us for a delay, which will be long enough
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* to configure things.
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*/
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writel(0x2800, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL));
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writel(regs->zq_config, AM33XX_EMIF4_0_REG(ZQ_CONFIG));
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writel(regs->sdram_config, CM_EMIF_SDRAM_CONFIG);
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writel(regs->sdram_config, AM33XX_EMIF4_0_REG(SDRAM_CONFIG));
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writel(regs->sdram_ref_ctrl,
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AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL));
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writel(regs->sdram_ref_ctrl,
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AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL_SHADOW));
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}
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writel(regs->sdram_ref_ctrl, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL));
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writel(regs->sdram_ref_ctrl, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL_SHADOW));
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writel(regs->sdram_config, AM33XX_EMIF4_0_REG(SDRAM_CONFIG));
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}
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/**
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* am335x_sdram_size - read back SDRAM size from sdram_config register
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*
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* @return: The SDRAM size
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*/
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unsigned long am335x_sdram_size(void)
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{
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int rows, cols, width, banks;
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unsigned long size;
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uint32_t sdram_config = readl(CM_EMIF_SDRAM_CONFIG);
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rows = ((sdram_config >> 7) & 0x7) + 9;
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cols = (sdram_config & 0x7) + 8;
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switch ((sdram_config >> 14) & 0x3) {
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case 0:
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width = 4;
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break;
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case 1:
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width = 2;
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break;
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default:
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return 0;
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}
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switch ((sdram_config >> 4) & 0x7) {
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case 0:
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banks = 1;
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break;
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case 1:
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banks = 2;
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break;
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case 2:
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banks = 4;
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break;
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case 3:
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banks = 8;
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break;
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default:
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return 0;
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}
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size = (1 << rows) * (1 << cols) * banks * width;
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debug("%s: sdram_config: 0x%08x cols: %2d rows: %2d width: %2d banks: %2d size: 0x%08lx\n",
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__func__, sdram_config, cols, rows, width, banks, size);
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return size;
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}
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void __noreturn am335x_barebox_entry(void *boarddata)
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{
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barebox_arm_entry(0x80000000, am335x_sdram_size(), boarddata);
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}
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void am33xx_config_io_ctrl(int ioctrl)
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{
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writel(ioctrl, AM33XX_DDR_CMD0_IOCTRL);
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writel(ioctrl, AM33XX_DDR_CMD1_IOCTRL);
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writel(ioctrl, AM33XX_DDR_CMD2_IOCTRL);
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writel(ioctrl, AM33XX_DDR_DATA0_IOCTRL);
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writel(ioctrl, AM33XX_DDR_DATA1_IOCTRL);
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}
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void am33xx_config_ddr_data(const struct am33xx_ddr_data *data, int macronr)
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{
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u32 base = 0x0;
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if (macronr)
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base = 0xA4;
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writel(data->rd_slave_ratio0, AM33XX_DATA0_RD_DQS_SLAVE_RATIO_0 + base);
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writel(data->wr_dqs_slave_ratio0, AM33XX_DATA0_WR_DQS_SLAVE_RATIO_0 + base);
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writel(data->wrlvl_init_ratio0, AM33XX_DATA0_WRLVL_INIT_RATIO_0 + base);
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writel(data->gatelvl_init_ratio0, AM33XX_DATA0_GATELVL_INIT_RATIO_0 + base);
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writel(data->fifo_we_slave_ratio0, AM33XX_DATA0_FIFO_WE_SLAVE_RATIO_0 + base);
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writel(data->wr_slave_ratio0, AM33XX_DATA0_WR_DATA_SLAVE_RATIO_0 + base);
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writel(data->use_rank0_delay, AM33XX_DATA0_RANK0_DELAYS_0 + base);
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writel(data->dll_lock_diff0, AM33XX_DATA0_DLL_LOCK_DIFF_0 + base);
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}
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void am335x_sdram_init(int ioctrl, const struct am33xx_cmd_control *cmd_ctrl,
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const struct am33xx_emif_regs *emif_regs,
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const struct am33xx_ddr_data *ddr_data)
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{
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uint32_t val;
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am33xx_enable_ddr_clocks();
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am33xx_config_vtp();
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am33xx_ddr_phydata_cmd_macro(cmd_ctrl);
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am33xx_config_ddr_data(ddr_data, 0);
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am33xx_config_ddr_data(ddr_data, 1);
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am33xx_config_io_ctrl(ioctrl);
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val = readl(AM33XX_DDR_IO_CTRL);
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val &= 0xefffffff;
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writel(val, AM33XX_DDR_IO_CTRL);
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val = readl(AM33XX_DDR_CKE_CTRL);
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val |= 0x00000001;
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writel(val, AM33XX_DDR_CKE_CTRL);
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am33xx_config_sdram(emif_regs);
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}
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#define AM33XX_CONTROL_SMA2_OFS 0x1320
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/**
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* am33xx_select_rmii2_crs_dv - Select RMII2_CRS_DV on GPMC_A9 pin in MODE3
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*/
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void am33xx_select_rmii2_crs_dv(void)
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{
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uint32_t val;
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if (am33xx_get_cpu_rev() == AM335X_ES1_0)
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return;
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val = readl(AM33XX_CTRL_BASE + AM33XX_CONTROL_SMA2_OFS);
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val |= 0x00000001;
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writel(val, AM33XX_CTRL_BASE + AM33XX_CONTROL_SMA2_OFS);
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}
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int am33xx_of_register_bootdevice(void)
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{
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struct device_d *dev;
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switch (bootsource_get()) {
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case BOOTSOURCE_MMC:
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if (bootsource_get_instance() == 0)
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dev = of_device_enable_and_register_by_name("mmc@48060000");
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else
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dev = of_device_enable_and_register_by_name("mmc@481d8000");
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break;
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case BOOTSOURCE_NAND:
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dev = of_device_enable_and_register_by_name("gpmc@50000000");
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break;
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case BOOTSOURCE_SPI:
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dev = of_device_enable_and_register_by_name("spi@48030000");
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break;
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case BOOTSOURCE_NET:
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dev = of_device_enable_and_register_by_name("ethernet@4a100000");
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break;
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default:
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/* Use nand fallback */
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dev = of_device_enable_and_register_by_name("gpmc@50000000");
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break;
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}
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if (!dev) {
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printf("Unable to register boot device\n");
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return -ENODEV;
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}
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return 0;
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}
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