Signed-off-by: Juergen Beisert <jbe@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
339 lines
8.7 KiB
C
339 lines
8.7 KiB
C
/*
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* Copyright (C) 2012 Juergen Beisert
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <config.h>
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#include <common.h>
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#include <init.h>
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#include <clock.h>
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#include <io.h>
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#include <asm-generic/div64.h>
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#include <mach/s3c-iomap.h>
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#include <mach/s3c-generic.h>
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#include <mach/s3c-clocks.h>
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/*
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* The main clock tree:
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*
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* ref_in
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* |
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* v
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* o-----------\
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* | MUX -o------------\
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* | / ^ | MUX --- DIV_APLL ------- ARMCLK -> CPU core
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* o--- APLL -- | | / |
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* | | o--/2 ------- |
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* | APLL_SEL | |<-MISC_CON_SYN667
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* | \ |
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* o-----------\ MUX-o-------\ |
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* | MUX--/ ^ | MUX --- DIV -o--------- HCLKx2 -> SDRAM (max. 266 MHz)
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* | / ^ | | / |
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* o---- MPLL-- | | o--/5 -- o-- DIV -- HCLK -> AXI / AHB (max. 133 MHz)
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* | | | |
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* | MPLL_SEL OTHERS_CLK_SELECT o-- DIV -- PCLK -> APB (max. 66 MHz)
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* |
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* o-----------\
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* | MUX---- to various hardware
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* | / ^
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* o---- EPLL-- EPLL_SEL
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*
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*/
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static unsigned s3c_get_apllclk(void)
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{
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uint32_t m, p, s, reg_val;
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if (!(readl(S3C_CLK_SRC) & S3C_CLK_SRC_FOUTAPLL))
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return S3C64XX_CLOCK_REFERENCE;
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reg_val = readl(S3C_APLLCON);
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if (!(reg_val & S3C_APLLCON_ENABLE))
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return 0;
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m = S3C_APLLCON_GET_MDIV(reg_val);
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p = S3C_APLLCON_GET_PDIV(reg_val);
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s = S3C_APLLCON_GET_SDIV(reg_val);
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return (S3C64XX_CLOCK_REFERENCE * m) / (p << s);
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}
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uint32_t s3c_get_mpllclk(void)
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{
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uint32_t m, p, s, reg_val;
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if (!(readl(S3C_CLK_SRC) & S3C_CLK_SRC_FOUTMPLL))
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return S3C64XX_CLOCK_REFERENCE;
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reg_val = readl(S3C_MPLLCON);
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if (!(reg_val & S3C_MPLLCON_ENABLE))
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return 0;
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m = S3C_MPLLCON_GET_MDIV(reg_val);
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p = S3C_MPLLCON_GET_PDIV(reg_val);
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s = S3C_MPLLCON_GET_SDIV(reg_val);
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return (S3C64XX_CLOCK_REFERENCE * m) / (p << s);
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}
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unsigned s3c_get_epllclk(void)
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{
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u32 m, p, s, k, reg0_val, reg1_val;
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u64 tmp;
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if (!(readl(S3C_CLK_SRC) & S3C_CLK_SRC_FOUTEPLL))
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return S3C64XX_CLOCK_REFERENCE;
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reg0_val = readl(S3C_EPLLCON0);
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if (!(reg0_val & S3C_EPLLCON0_ENABLE))
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return 0; /* PLL is disabled */
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reg1_val = readl(S3C_EPLLCON1);
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m = S3C_EPLLCON0_GET_MDIV(reg0_val);
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p = S3C_EPLLCON0_GET_PDIV(reg0_val);
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s = S3C_EPLLCON0_GET_SDIV(reg0_val);
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k = S3C_EPLLCON1_GET_KDIV(reg1_val);
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tmp = S3C64XX_CLOCK_REFERENCE;
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tmp *= (m << 16) + k;
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do_div(tmp, (p << s));
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return (unsigned)(tmp >> 16);
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}
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unsigned s3c_set_epllclk(unsigned m, unsigned p, unsigned s, unsigned k)
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{
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u32 con0, con1, src = readl(S3C_CLK_SRC) & ~S3C_CLK_SRC_FOUTEPLL;
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/* do not use the EPLL clock when it is in transit to the new frequency */
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writel(src, S3C_CLK_SRC);
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con0 = S3C_EPLLCON0_SET_MDIV(m) | S3C_EPLLCON0_SET_PDIV(p) |
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S3C_EPLLCON0_SET_SDIV(s) | S3C_EPLLCON0_ENABLE;
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con1 = S3C_EPLLCON1_SET_KDIV(k);
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/*
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* After changing the multiplication value 'm' the PLL output will
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* be masked for the time set in the EPLL_LOCK register until it
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* settles to the new frequency. EPLL_LOCK contains a value for a
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* simple counter which counts the external reference clock.
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*/
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writel(con0, S3C_EPLLCON0);
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writel(con1, S3C_EPLLCON1);
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udelay((1000000000 / S3C64XX_CLOCK_REFERENCE)
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* (S3C_EPLL_LOCK_PLL_LOCKTIME(readl(S3C_EPLL_LOCK)) + 1) / 1000);
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/* enable the EPLL's clock output to the system */
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writel(src | S3C_CLK_SRC_FOUTEPLL, S3C_CLK_SRC);
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return s3c_get_epllclk();
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}
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uint32_t s3c_get_fclk(void)
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{
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unsigned clk;
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clk = s3c_get_apllclk();
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if (readl(S3C_MISC_CON) & S3C_MISC_CON_SYN667)
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clk /= 2;
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return clk / (S3C_CLK_DIV0_GET_ADIV(readl(S3C_CLK_DIV0)) + 1);
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}
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static unsigned s3c_get_hclk_in(void)
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{
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unsigned clk;
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if (readl(S3C_OTHERS) & S3C_OTHERS_CLK_SELECT)
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clk = s3c_get_apllclk();
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else
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clk = s3c_get_mpllclk();
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if (readl(S3C_MISC_CON) & S3C_MISC_CON_SYN667)
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clk /= 5;
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return clk;
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}
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static unsigned s3c_get_hclkx2(void)
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{
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return s3c_get_hclk_in() /
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(S3C_CLK_DIV0_GET_HCLK2(readl(S3C_CLK_DIV0)) + 1);
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}
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uint32_t s3c_get_hclk(void)
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{
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return s3c_get_hclkx2() /
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(S3C_CLK_DIV0_GET_HCLK(readl(S3C_CLK_DIV0)) + 1);
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}
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uint32_t s3c_get_pclk(void)
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{
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return s3c_get_hclkx2() /
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(S3C_CLK_DIV0_GET_PCLK(readl(S3C_CLK_DIV0)) + 1);
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}
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static void s3c_init_mpll_dout(void)
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{
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unsigned reg;
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/* keep it at the same frequency as HCLKx2 */
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reg = readl(S3C_CLK_DIV0) | S3C_CLK_DIV0_SET_MPLL_DIV(1); /* e.g. / 2 */
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writel(reg, S3C_CLK_DIV0);
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}
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/* configure and enable UCLK1 */
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static int s3c_init_uart_clock(void)
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{
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unsigned reg;
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s3c_init_mpll_dout(); /* to have a reliable clock source */
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/* source the UART clock from the MPLL, currently *not* from EPLL */
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reg = readl(S3C_CLK_SRC) | S3C_CLK_SRC_UARTMPLL;
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writel(reg, S3C_CLK_SRC);
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/* keep UART clock at the same frequency than the PCLK */
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reg = readl(S3C_CLK_DIV2) & ~S3C_CLK_DIV2_UART_MASK;
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reg |= S3C_CLK_DIV2_SET_UART(0x3); /* / 4 */
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writel(reg, S3C_CLK_DIV2);
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/* ensure this very special clock is running */
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reg = readl(S3C_SCLK_GATE) | S3C_SCLK_GATE_UART;
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writel(reg, S3C_SCLK_GATE);
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return 0;
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}
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core_initcall(s3c_init_uart_clock);
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/* UART source selection
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* The UART related clock path: |
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* v
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* PCLK --------------------------------------o-----0-\
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* ???? -------------------------------UCLK0--|-----1--\MUX----- UART
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* MPLL -----DIV0------\ +-----2--/
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* MUX---DIV2------UCLK1--------3-/
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* EPLL ---------------/
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* ^SRC_UARTMPLL
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*/
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unsigned s3c_get_uart_clk(unsigned source)
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{
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u32 reg;
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unsigned clk, pdiv, uartpdiv;
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switch (source) {
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default: /* PCLK */
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clk = s3c_get_pclk();
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pdiv = uartpdiv = 1;
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break;
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case 1: /* UCLK0 */
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clk = 0;
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pdiv = uartpdiv = 1; /* TODO */
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break;
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case 3: /* UCLK1 */
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reg = readl(S3C_CLK_SRC);
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if (reg & S3C_CLK_SRC_UARTMPLL) {
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clk = s3c_get_mpllclk();
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pdiv = S3C_CLK_DIV0_GET_MPLL_DIV(readl(S3C_CLK_DIV0)) + 1;
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} else {
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clk = s3c_get_epllclk();
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pdiv = 1;
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}
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uartpdiv = S3C_CLK_DIV2_GET_UART(readl(S3C_CLK_DIV2)) + 1;
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break;
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}
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return clk / pdiv / uartpdiv;
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}
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/*
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* The MMC related clock path:
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*
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* MMCx_SEL
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* |
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* v
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* EPLLout --------0-\
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* MPLLout --DIV0--1--\-------SCLK_MMCx----DIV_MMCx------>HSMMCx
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* EPLLin --------2--/ on/off / 1..16
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* 27 MHz --------3-/
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*
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* The datasheet is not very precise here, so the schematic shown above was
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* made by checking various bits in the SYSCON.
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*/
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unsigned s3c_get_hsmmc_clk(int id)
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{
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u32 sel, div, sclk = readl(S3C_SCLK_GATE);
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unsigned bclk;
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if (!(sclk & S3C_SCLK_GATE_MMC(id)))
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return 0; /* disabled */
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sel = S3C_CLK_SRC_GET_MMC_SEL(id, readl(S3C_CLK_SRC));
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switch (sel) {
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case 0:
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bclk = s3c_get_epllclk();
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break;
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case 1:
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bclk = s3c_get_mpllclk();
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bclk >>= S3C_CLK_DIV0_GET_MPLL_DIV(readl(S3C_CLK_DIV0));
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break;
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case 2:
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bclk = S3C64XX_CLOCK_REFERENCE;
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break;
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case 3:
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bclk = 27000000;
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break;
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}
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div = S3C_CLK_DIV0_GET_MMC(id, readl(S3C_CLK_DIV0)) + 1;
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return bclk / div;
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}
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void s3c_set_hsmmc_clk(int id, int src, unsigned div)
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{
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u32 reg;
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if (!div)
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div = 1;
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writel(readl(S3C_SCLK_GATE) & ~S3C_SCLK_GATE_MMC(id), S3C_SCLK_GATE);
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/* select the new clock source */
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reg = readl(S3C_CLK_SRC) & ~S3C_CLK_SRC_SET_MMC_SEL(id, ~0);
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reg |= S3C_CLK_SRC_SET_MMC_SEL(id, src);
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writel(reg, S3C_CLK_SRC);
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/* select the new pre-divider */
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reg = readl(S3C_CLK_DIV0) & ~ S3C_CLK_DIV0_SET_MMC(id, ~0);
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reg |= S3C_CLK_DIV0_SET_MMC(id, div - 1);
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writel(reg, S3C_CLK_DIV0);
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/* calling this function implies enabling of the clock */
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writel(readl(S3C_SCLK_GATE) | S3C_SCLK_GATE_MMC(id), S3C_SCLK_GATE);
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}
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int s3c64xx_dump_clocks(void)
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{
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printf("refclk: %7d kHz\n", S3C64XX_CLOCK_REFERENCE / 1000);
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printf("apll: %7d kHz\n", s3c_get_apllclk() / 1000);
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printf("mpll: %7d kHz\n", s3c_get_mpllclk() / 1000);
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printf("epll: %7d kHz\n", s3c_get_epllclk() / 1000);
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printf("CPU: %7d kHz\n", s3c_get_fclk() / 1000);
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printf("hclkx2: %7d kHz\n", s3c_get_hclkx2() / 1000);
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printf("hclk: %7d kHz\n", s3c_get_hclk() / 1000);
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printf("pclk: %7d kHz\n", s3c_get_pclk() / 1000);
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return 0;
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}
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late_initcall(s3c64xx_dump_clocks);
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