103 lines
2.9 KiB
C
103 lines
2.9 KiB
C
/*
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* Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
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*
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* Based on Linux clk driver:
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* Copyright (c) 2014 MundoReader S.L.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <asm/io.h>
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#include <common.h>
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#include <mach/rockchip-regs.h>
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#define RK3188_CLK_BASE 0x20000000
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#define RK3188_PLL_LOCK_REG 0x200080ac
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#define PLL_MODE_MASK 0x3
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#define PLL_MODE_SLOW 0x0
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#define PLL_MODE_NORM 0x1
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#define PLL_MODE_DEEP 0x2
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#define PLL_RESET_DELAY(nr) ((nr * 500) / 24 + 1)
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#define PLLCON0_OD_MASK 0xf
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#define PLLCON0_OD_SHIFT 0
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#define PLLCON0_NR_MASK 0x3f
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#define PLLCON0_NR_SHIFT 8
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#define PLLCON1_NF_MASK 0x1fff
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#define PLLCON1_NF_SHIFT 0
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#define PLLCON2_BWADJ_MASK 0xfff
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#define PLLCON2_BWADJ_SHIFT 0
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#define PLLCON3_RESET (1 << 1)
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#define PLLCON3_BYPASS (1 << 0)
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struct rockchip_pll_data {
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int con_base;
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int mode_offset;
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int mode_shift;
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int lock_shift;
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};
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struct rockchip_pll_data rk3188_plls[] = {
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{ 0x00, 0x40, 0x00, 0x06 },
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{ 0x10, 0x40, 0x04, 0x05 },
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{ 0x20, 0x40, 0x08, 0x07 },
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{ 0x30, 0x40, 0x0c, 0x08 },
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};
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#define HIWORD_UPDATE(val, mask, shift) \
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((val) << (shift) | (mask) << ((shift) + 16))
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int rk3188_pll_set_parameters(int pll, int nr, int nf, int no)
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{
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struct rockchip_pll_data *d = &rk3188_plls[pll];
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int delay = 0;
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debug("rk3188 pll %d: set param %d %d %d\n", pll, nr, nf, no);
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/* pull pll in slow mode */
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writel(HIWORD_UPDATE(PLL_MODE_SLOW, PLL_MODE_MASK, d->mode_shift),
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RK3188_CLK_BASE + d->mode_offset);
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/* enter reset */
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writel(HIWORD_UPDATE(PLLCON3_RESET, PLLCON3_RESET, 0),
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RK3188_CLK_BASE + d->con_base + 12);
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/* update pll values */
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writel(HIWORD_UPDATE(nr - 1, PLLCON0_NR_MASK, PLLCON0_NR_SHIFT) |
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HIWORD_UPDATE(no - 1, PLLCON0_OD_MASK, PLLCON0_OD_SHIFT),
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RK3188_CLK_BASE + d->con_base + 0);
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writel(HIWORD_UPDATE(nf - 1, PLLCON1_NF_MASK, PLLCON1_NF_SHIFT),
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RK3188_CLK_BASE + d->con_base + 4);
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writel(HIWORD_UPDATE(nf >> 1, PLLCON2_BWADJ_MASK, PLLCON2_BWADJ_SHIFT),
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RK3188_CLK_BASE + d->con_base + 8);
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/* leave reset and wait the reset_delay */
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writel(HIWORD_UPDATE(0, PLLCON3_RESET, 0),
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RK3188_CLK_BASE + d->con_base + 12);
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udelay(PLL_RESET_DELAY(nr));
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/* wait for the pll to lock */
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while (delay++ < 24000000) {
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if (readl(RK3188_PLL_LOCK_REG) & BIT(d->lock_shift))
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break;
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}
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/* go back to normal mode */
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writel(HIWORD_UPDATE(PLL_MODE_NORM, PLL_MODE_MASK, d->mode_shift),
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RK3188_CLK_BASE + d->mode_offset);
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return 0;
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}
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EXPORT_SYMBOL(rk3188_pll_set_parameters);
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