165 lines
3.4 KiB
C
165 lines
3.4 KiB
C
/*
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* Processor capabilities determination functions.
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*
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* Copyright (C) xxxx the Anonymous
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* Copyright (C) 1994 - 2006 Ralf Baechle
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* Copyright (C) 2003, 2004 Maciej W. Rozycki
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* Copyright (C) 2001, 2004 MIPS Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <common.h>
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#include <asm/mipsregs.h>
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#include <asm/cpu-info.h>
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#include <asm/cpu.h>
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const char *__cpu_name;
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struct cpuinfo_mips cpu_data[1];
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static char unknown_isa[] = KERN_ERR \
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"Unsupported ISA type, c0.config0: %d.";
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static inline unsigned int decode_config0(struct cpuinfo_mips *c)
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{
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unsigned int config0;
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int isa;
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config0 = read_c0_config();
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if (((config0 & MIPS_CONF_MT) >> 7) == 1)
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c->options |= MIPS_CPU_TLB;
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isa = (config0 & MIPS_CONF_AT) >> 13;
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switch (isa) {
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case 0:
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switch ((config0 & MIPS_CONF_AR) >> 10) {
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case 0:
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c->isa_level = MIPS_CPU_ISA_M32R1;
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break;
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case 1:
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c->isa_level = MIPS_CPU_ISA_M32R2;
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break;
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default:
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goto unknown;
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}
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break;
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case 2:
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switch ((config0 & MIPS_CONF_AR) >> 10) {
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case 0:
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c->isa_level = MIPS_CPU_ISA_M64R1;
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break;
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case 1:
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c->isa_level = MIPS_CPU_ISA_M64R2;
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break;
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default:
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goto unknown;
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}
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break;
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default:
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goto unknown;
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}
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return config0 & MIPS_CONF_M;
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unknown:
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panic(unknown_isa, config0);
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}
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static void decode_configs(struct cpuinfo_mips *c)
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{
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int ok;
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/* MIPS32 or MIPS64 compliant CPU. */
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c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
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MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
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c->scache.flags = MIPS_CACHE_NOT_PRESENT;
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ok = decode_config0(c); /* Read Config registers. */
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BUG_ON(!ok); /* Arch spec violation! */
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}
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static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
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{
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switch (c->processor_id & PRID_IMP_MASK) {
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case PRID_IMP_LOONGSON1:
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decode_configs(c);
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c->cputype = CPU_LOONGSON1;
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switch (c->processor_id & PRID_REV_MASK) {
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case PRID_REV_LOONGSON1B:
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__cpu_name = "Loongson 1B";
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break;
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}
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break;
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}
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}
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static inline void cpu_probe_mips(struct cpuinfo_mips *c)
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{
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decode_configs(c);
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switch (c->processor_id & 0xff00) {
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case PRID_IMP_24K:
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case PRID_IMP_24KE:
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c->cputype = CPU_24K;
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__cpu_name = "MIPS 24Kc";
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break;
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}
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}
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static inline void cpu_probe_broadcom(struct cpuinfo_mips *c)
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{
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decode_configs(c);
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switch (c->processor_id & 0xff00) {
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case PRID_IMP_BMIPS3300:
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c->cputype = CPU_BMIPS3300;
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__cpu_name = "Broadcom BMIPS3300";
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break;
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}
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}
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static inline void cpu_probe_ingenic(struct cpuinfo_mips *c)
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{
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decode_configs(c);
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/* JZRISC does not implement the CP0 counter. */
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c->options &= ~MIPS_CPU_COUNTER;
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switch (c->processor_id & 0xff00) {
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case PRID_IMP_JZRISC:
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c->cputype = CPU_JZRISC;
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__cpu_name = "Ingenic JZRISC";
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break;
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default:
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panic("Unknown Ingenic Processor ID!");
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break;
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}
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}
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void cpu_probe(void)
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{
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struct cpuinfo_mips *c = ¤t_cpu_data;
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c->processor_id = PRID_IMP_UNKNOWN;
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c->fpu_id = FPIR_IMP_NONE;
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c->cputype = CPU_UNKNOWN;
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c->processor_id = read_c0_prid();
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switch (c->processor_id & 0xff0000) {
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case PRID_COMP_LEGACY:
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cpu_probe_legacy(c);
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break;
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case PRID_COMP_MIPS:
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cpu_probe_mips(c);
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break;
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case PRID_COMP_BROADCOM:
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cpu_probe_broadcom(c);
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break;
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case PRID_COMP_INGENIC:
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cpu_probe_ingenic(c);
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break;
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}
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}
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