128 lines
3.2 KiB
C
128 lines
3.2 KiB
C
/*
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* Copyright 2012 GE Intelligent Platforms, Inc.
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*
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* Copyright 2004, 2007-2011 Freescale Semiconductor, Inc.
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*
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* (C) Copyright 2003 Motorola Inc.
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* Xianghua Xiao, (X.Xiao@motorola.com)
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*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <common.h>
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#include <asm/processor.h>
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#include <mach/clock.h>
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#include <mach/immap_85xx.h>
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#include <mach/mpc85xx.h>
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void fsl_get_sys_info(struct sys_info *sysInfo)
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{
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void __iomem *gur = (void __iomem *)(MPC85xx_GUTS_ADDR);
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uint plat_ratio, e500_ratio, half_freqSystemBus;
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uint lcrr_div;
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int i;
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plat_ratio = in_be32(gur + MPC85xx_GUTS_PORPLLSR_OFFSET) & 0x0000003e;
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plat_ratio >>= 1;
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sysInfo->freqSystemBus = plat_ratio * CFG_SYS_CLK_FREQ;
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/*
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* Divide before multiply to avoid integer
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* overflow for processor speeds above 2GHz.
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*/
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half_freqSystemBus = sysInfo->freqSystemBus/2;
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for (i = 0; i < fsl_cpu_numcores(); i++) {
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e500_ratio = (in_be32(gur + MPC85xx_GUTS_PORPLLSR_OFFSET) >>
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(i * 8 + 16)) & 0x3f;
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sysInfo->freqProcessor[i] = e500_ratio * half_freqSystemBus;
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}
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/* Note: freqDDRBus is the MCLK frequency, not the data rate. */
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sysInfo->freqDDRBus = sysInfo->freqSystemBus;
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#ifdef CFG_DDR_CLK_FREQ
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{
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u32 ddr_ratio = (in_be32(gur + MPC85xx_GUTS_PORPLLSR_OFFSET) &
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MPC85xx_PORPLLSR_DDR_RATIO) >>
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MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
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if (ddr_ratio != 0x7)
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sysInfo->freqDDRBus = ddr_ratio * CFG_DDR_CLK_FREQ;
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}
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#endif
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lcrr_div = in_be32(LBC_BASE_ADDR + FSL_LBC_LCCR) & LCRR_CLKDIV;
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if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) {
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/*
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* The entire PQ38 family use the same bit-representation
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* for twice the clock divider values.
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*/
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lcrr_div *= 2;
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sysInfo->freqLocalBus = sysInfo->freqSystemBus / lcrr_div;
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} else {
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/* In case anyone cares what the unknown value is */
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sysInfo->freqLocalBus = lcrr_div;
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}
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}
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unsigned long fsl_get_bus_freq(ulong dummy)
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{
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struct sys_info sys_info;
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fsl_get_sys_info(&sys_info);
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return sys_info.freqSystemBus;
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}
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unsigned long fsl_get_ddr_freq(ulong dummy)
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{
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struct sys_info sys_info;
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fsl_get_sys_info(&sys_info);
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return sys_info.freqDDRBus;
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}
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unsigned long fsl_get_timebase_clock(void)
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{
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struct sys_info sysinfo;
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fsl_get_sys_info(&sysinfo);
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return (sysinfo.freqSystemBus + 4UL)/8UL;
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}
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unsigned long fsl_get_i2c_freq(void)
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{
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uint svr;
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struct sys_info sysinfo;
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void __iomem *gur = IOMEM(MPC85xx_GUTS_ADDR);
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fsl_get_sys_info(&sysinfo);
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svr = get_svr();
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if ((svr == SVR_8544) || (svr == SVR_8544_E)) {
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if (in_be32(gur + MPC85xx_GUTS_PORDEVSR2_OFFSET) &
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MPC85xx_PORDEVSR2_SEC_CFG)
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return sysinfo.freqSystemBus / 3;
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}
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return sysinfo.freqSystemBus / 2;
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}
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