143 lines
3.2 KiB
C
143 lines
3.2 KiB
C
/*
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* Copyright (C) 2013 Jean-Christophe PLAGNIOL-VILLARD <plagnio@jcrosoft.com>
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*
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* GPLv2 only
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*/
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#include <common.h>
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#include <init.h>
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#include <asm/armlinux.h>
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#include <asm/system_info.h>
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#include <generated/mach-types.h>
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#include <mach/devices.h>
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#include <mach/hardware.h>
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#include <mach/sysregs.h>
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#include <environment.h>
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#include <partition.h>
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#include <sizes.h>
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#include <io.h>
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#include <of.h>
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#define FIRMWARE_DTB_BASE 0x1000
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#define HB_OPP_VERSION 0
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struct fdt_header *fdt = NULL;
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static int hb_fixup(struct device_node *root, void *unused)
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{
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struct device_node *node;
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u32 reg = readl(sregs_base + HB_SREG_A9_PWRDOM_DATA);
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u32 *opp_table = (u32 *)HB_SYSRAM_OPP_TABLE_BASE;
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u32 dtb_table[2*10];
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u32 i;
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u32 num_opps;
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__be32 latency;
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if (!(reg & HB_PWRDOM_STAT_SATA)) {
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for_each_compatible_node(node, NULL, "calxeda,hb-ahci")
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of_set_property(node, "status", "disabled",
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sizeof("disabled"), 1);
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}
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if (!(reg & HB_PWRDOM_STAT_EMMC)) {
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for_each_compatible_node(node, NULL, "calxeda,hb-sdhci")
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of_set_property(node, "status", "disabled",
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sizeof("disabled"), 1);
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}
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if ((opp_table[0] >> 16) != HB_OPP_VERSION)
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return 0;
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node = of_find_node_by_path("/cpus/cpu@0");
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if (!node)
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return 0;
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num_opps = opp_table[0] & 0xff;
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for (i = 0; i < num_opps; i++) {
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dtb_table[2 * i] = cpu_to_be32(opp_table[3 + 3 * i]);
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dtb_table[2 * i + 1] = cpu_to_be32(opp_table[2 + 3 * i]);
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}
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latency = cpu_to_be32(opp_table[1]);
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of_set_property(node, "transition-latency", &latency, 4, 1);
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of_set_property(node, "operating-points", dtb_table, 8 * num_opps, 1);
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return 0;
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}
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static int highbank_mem_init(void)
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{
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struct device_node *root, *np;
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int ret;
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/* load by the firmware at 0x1000 */
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fdt = IOMEM(FIRMWARE_DTB_BASE);
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root = of_unflatten_dtb(fdt);
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if (!root) {
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pr_warn("no dtb found at 0x1000 use default configuration\n");
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fdt = NULL;
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goto not_found;
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}
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of_set_root_node(root);
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np = of_find_node_by_path("/memory");
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if (!np) {
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pr_warn("no memory node use default configuration\n");
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goto not_found;
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}
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ret = of_add_memory(np, true);
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if (ret) {
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pr_warn("memory node: probe failed use default configuration\n");
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goto not_found;
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}
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pr_info("highbank: dtb probed memory size\n");
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return 0;
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not_found:
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highbank_add_ddram(4089 << 20);
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return 0;
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}
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mem_initcall(highbank_mem_init);
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static int highbank_devices_init(void)
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{
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of_register_fixup(hb_fixup, NULL);
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if (!fdt) {
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highbank_register_gpio(0);
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highbank_register_gpio(1);
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highbank_register_gpio(2);
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highbank_register_gpio(3);
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highbank_register_ahci();
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highbank_register_xgmac(0);
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highbank_register_xgmac(1);
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} else {
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fdt = of_get_fixed_tree(NULL);
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add_mem_device("dtb", (unsigned long)fdt, be32_to_cpu(fdt->totalsize),
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IORESOURCE_MEM_WRITEABLE);
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devfs_add_partition("ram0", FIRMWARE_DTB_BASE, SZ_64K, DEVFS_PARTITION_FIXED, "firmware-dtb");
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}
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devfs_add_partition("nvram", 0x00000, SZ_16K, DEVFS_PARTITION_FIXED, "env0");
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return 0;
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}
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device_initcall(highbank_devices_init);
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static int highbank_console_init(void)
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{
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barebox_set_model("Calxeda Highbank");
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barebox_set_hostname("highbank");
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highbank_register_uart();
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return 0;
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}
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console_initcall(highbank_console_init);
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