226 lines
5.5 KiB
C
226 lines
5.5 KiB
C
#include <common.h>
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#include <gpio.h>
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#include <init.h>
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#include <mach/hardware.h>
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#include <mach/at91_pmc.h>
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#include <mach/io.h>
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#include <mach/cpu.h>
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#include "soc.h"
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#include "generic.h"
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#include "clock.h"
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/* --------------------------------------------------------------------
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* Clocks
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* -------------------------------------------------------------------- */
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/*
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* The peripheral clocks.
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*/
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static struct clk pioAB_clk = {
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.name = "pioAB_clk",
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.pmc_mask = 1 << AT91SAM9N12_ID_PIOAB,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk pioCD_clk = {
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.name = "pioCD_clk",
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.pmc_mask = 1 << AT91SAM9N12_ID_PIOCD,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk usart0_clk = {
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.name = "usart0_clk",
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.pmc_mask = 1 << AT91SAM9N12_ID_USART0,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk usart1_clk = {
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.name = "usart1_clk",
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.pmc_mask = 1 << AT91SAM9N12_ID_USART1,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk usart2_clk = {
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.name = "usart2_clk",
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.pmc_mask = 1 << AT91SAM9N12_ID_USART2,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk usart3_clk = {
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.name = "usart3_clk",
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.pmc_mask = 1 << AT91SAM9N12_ID_USART3,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk twi0_clk = {
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.name = "twi0_clk",
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.pmc_mask = 1 << AT91SAM9N12_ID_TWI0,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk twi1_clk = {
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.name = "twi1_clk",
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.pmc_mask = 1 << AT91SAM9N12_ID_TWI1,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk mmc_clk = {
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.name = "mci_clk",
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.pmc_mask = 1 << AT91SAM9N12_ID_MCI,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk spi0_clk = {
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.name = "spi0_clk",
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.pmc_mask = 1 << AT91SAM9N12_ID_SPI0,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk spi1_clk = {
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.name = "spi1_clk",
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.pmc_mask = 1 << AT91SAM9N12_ID_SPI1,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk uart0_clk = {
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.name = "uart0_clk",
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.pmc_mask = 1 << AT91SAM9N12_ID_UART0,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk uart1_clk = {
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.name = "uart1_clk",
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.pmc_mask = 1 << AT91SAM9N12_ID_UART1,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk tcb0_clk = {
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.name = "tcb0_clk",
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.pmc_mask = 1 << AT91SAM9N12_ID_TCB,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk pwm_clk = {
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.name = "pwm_clk",
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.pmc_mask = 1 << AT91SAM9N12_ID_PWM,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk adc_clk = {
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.name = "adc_clk",
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.pmc_mask = 1 << AT91SAM9N12_ID_ADC,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk dma_clk = {
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.name = "dma_clk",
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.pmc_mask = 1 << AT91SAM9N12_ID_DMA,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk uhpfs_clk = {
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.name = "uhpfs_clk",
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.pmc_mask = 1 << AT91SAM9N12_ID_UHPFS,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk udc_clk = {
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.name = "udc_clk",
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.pmc_mask = 1 << AT91SAM9N12_ID_UDPFS,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk lcdc_clk = {
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.name = "lcdc_clk",
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.pmc_mask = 1 << AT91SAM9N12_ID_LCDC,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk ssc_clk = {
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.name = "ssc_clk",
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.pmc_mask = 1 << AT91SAM9N12_ID_SSC,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk *periph_clocks[] __initdata = {
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&pioAB_clk,
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&pioCD_clk,
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&usart0_clk,
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&usart1_clk,
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&usart2_clk,
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&usart3_clk,
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&twi0_clk,
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&twi1_clk,
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&mmc_clk,
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&spi0_clk,
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&spi1_clk,
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&uart0_clk,
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&uart1_clk,
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&tcb0_clk,
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&pwm_clk,
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&adc_clk,
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&dma_clk,
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&lcdc_clk,
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&uhpfs_clk,
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&udc_clk,
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&ssc_clk,
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};
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static struct clk_lookup periph_clocks_lookups[] = {
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CLKDEV_CON_ID("ohci_clk", &uhpfs_clk),
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CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi0", &spi0_clk),
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CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi1", &spi1_clk),
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CLKDEV_DEV_ID("at91sam9x5-gpio0", &pioAB_clk),
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CLKDEV_DEV_ID("at91sam9x5-gpio1", &pioAB_clk),
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CLKDEV_DEV_ID("at91sam9x5-gpio2", &pioCD_clk),
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CLKDEV_DEV_ID("at91sam9x5-gpio3", &pioCD_clk),
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CLKDEV_DEV_ID("at91-pit", &mck),
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CLKDEV_CON_DEV_ID("hck1", "atmel_hlcdfb", &lcdc_clk),
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};
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static struct clk_lookup usart_clocks_lookups[] = {
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CLKDEV_CON_DEV_ID("usart", "atmel_usart0", &mck),
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CLKDEV_CON_DEV_ID("usart", "atmel_usart1", &usart0_clk),
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CLKDEV_CON_DEV_ID("usart", "atmel_usart2", &usart1_clk),
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CLKDEV_CON_DEV_ID("usart", "atmel_usart3", &usart2_clk),
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CLKDEV_CON_DEV_ID("usart", "atmel_usart4", &usart3_clk),
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};
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/*
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* The two programmable clocks.
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* You must configure pin multiplexing to bring these signals out.
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*/
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static struct clk pck0 = {
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.name = "pck0",
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.pmc_mask = AT91_PMC_PCK0,
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.type = CLK_TYPE_PROGRAMMABLE,
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.id = 0,
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};
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static struct clk pck1 = {
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.name = "pck1",
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.pmc_mask = AT91_PMC_PCK1,
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.type = CLK_TYPE_PROGRAMMABLE,
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.id = 1,
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};
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static void __init at91sam9n12_register_clocks(void)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
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clk_register(periph_clocks[i]);
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clk_register(&pck0);
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clk_register(&pck1);
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clkdev_add_table(periph_clocks_lookups,
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ARRAY_SIZE(periph_clocks_lookups));
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clkdev_add_table(usart_clocks_lookups,
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ARRAY_SIZE(usart_clocks_lookups));
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}
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/* --------------------------------------------------------------------
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* AT91SAM9N12 processor initialization
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* -------------------------------------------------------------------- */
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static void at91sam9n12_initialize(void)
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{
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/* Register the processor-specific clocks */
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at91sam9n12_register_clocks();
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/* Register GPIO subsystem */
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at91_add_sam9x5_gpio(0, AT91SAM9N12_BASE_PIOA);
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at91_add_sam9x5_gpio(1, AT91SAM9N12_BASE_PIOB);
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at91_add_sam9x5_gpio(2, AT91SAM9N12_BASE_PIOC);
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at91_add_sam9x5_gpio(3, AT91SAM9N12_BASE_PIOD);
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at91_add_pit(AT91SAM9N12_BASE_PIT);
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at91_add_sam9_smc(DEVICE_ID_SINGLE, AT91SAM9N12_BASE_SMC, 0x200);
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}
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AT91_SOC_START(sam9n12)
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.init = at91sam9n12_initialize,
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AT91_SOC_END
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