OpenRISC is the original flagship project of the OpenCores community. This project aims to develop a series of general purpose open source RISC CPU architectures. A team from OpenCores provided the first implementation, the OpenRISC 1200, written in the Verilog hardware description language. Even though I should have created an mach-or1200 directory, it is not necessary for now. The OpenRISC 1200 CPU is the only one available and it will be for some time. Signed-off-by: Franck Jullien <franck.jullien@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
30 lines
438 B
Text
30 lines
438 B
Text
config OPENRISC
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bool
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select HAVE_CONFIGURABLE_MEMORY_LAYOUT
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default y
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# not used
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config ARCH_TEXT_BASE
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hex
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default 0x00000000
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config BOARDINFO
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default "Openrisc simulator" if GENERIC
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choice
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prompt "Select your board"
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config GENERIC
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bool "Generic "
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select OPENRISC
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endchoice
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source common/Kconfig
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source commands/Kconfig
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source net/Kconfig
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source drivers/Kconfig
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source fs/Kconfig
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source lib/Kconfig
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source crypto/Kconfig
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