To allow for some generic io accessors introduce io.h and use this instead of asm/io.h throughout the tree. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
261 lines
7.7 KiB
C
261 lines
7.7 KiB
C
/*
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* Copyright (C) 2010 Michael Grzeschik <mgr@pengutronix.de>
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*
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* This file is released under the GPLv2
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*
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*/
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/*
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* OMAP USBHOST Register addresses: VIRTUAL ADDRESSES
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*/
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/*-------------------------------------------------------------------------*/
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#include <mfd/twl4030.h>
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#include <usb/twl4030.h>
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#include <mach/ehci.h>
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#include <common.h>
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#include <io.h>
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#include <clock.h>
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#include <gpio.h>
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#include <mach/omap3-silicon.h>
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#include <mach/omap3-clock.h>
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#include <mach/cm-regbits-34xx.h>
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#include <mach/sys_info.h>
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void omap_usb_utmi_init(struct omap_hcd *omap, u8 tll_channel_mask)
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{
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unsigned reg;
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int i;
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/* Program the 3 TLL channels upfront */
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for (i = 0; i < OMAP_TLL_CHANNEL_COUNT; i++) {
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reg = __raw_readl(OMAP_USBTLL_BASE + OMAP_TLL_CHANNEL_CONF(i));
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/* Disable AutoIdle, BitStuffing and use SDR Mode */
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reg &= ~(OMAP_TLL_CHANNEL_CONF_UTMIAUTOIDLE
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| OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF
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| OMAP_TLL_CHANNEL_CONF_ULPIDDRMODE);
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__raw_writel(reg, OMAP_USBTLL_BASE + OMAP_TLL_CHANNEL_CONF(i));
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}
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/* Program Common TLL register */
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reg = __raw_readl(OMAP_USBTLL_BASE + OMAP_TLL_SHARED_CONF);
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reg |= (OMAP_TLL_SHARED_CONF_FCLK_IS_ON
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| OMAP_TLL_SHARED_CONF_USB_DIVRATION
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| OMAP_TLL_SHARED_CONF_USB_180D_SDR_EN);
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reg &= ~OMAP_TLL_SHARED_CONF_USB_90D_DDR_EN;
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__raw_writel(reg, OMAP_USBTLL_BASE + OMAP_TLL_SHARED_CONF);
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/* Enable channels now */
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for (i = 0; i < OMAP_TLL_CHANNEL_COUNT; i++) {
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reg = __raw_readl(OMAP_USBTLL_BASE + OMAP_TLL_CHANNEL_CONF(i));
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/* Enable only the reg that is needed */
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if (!(tll_channel_mask & 1<<i))
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continue;
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reg |= OMAP_TLL_CHANNEL_CONF_CHANEN;
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__raw_writel(reg, OMAP_USBTLL_BASE + OMAP_TLL_CHANNEL_CONF(i));
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__raw_writeb(0xbe,
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OMAP_USBTLL_BASE + OMAP_TLL_ULPI_SCRATCH_REGISTER(i));
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}
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}
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int ehci_omap_init(struct omap_hcd *omap)
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{
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uint64_t start;
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int timeout = 1000;
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u8 tll_ch_mask = 0;
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u32 v = 0;
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if (twl4030_usb_ulpi_init()) {
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printf("ERROR: %s Could not initialize PHY\n",
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__PRETTY_FUNCTION__);
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return -EINVAL;
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}
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v = __raw_readl(CM_REG(CLKSEL4_PLL));
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v |= (12 << OMAP3430ES2_PERIPH2_DPLL_DIV_SHIFT);
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v |= (120 << OMAP3430ES2_PERIPH2_DPLL_MULT_SHIFT);
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__raw_writel(v, CM_REG(CLKSEL4_PLL));
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v = __raw_readl(CM_REG(CLKSEL5_PLL));
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v |= (1 << OMAP3430ES2_DIV_120M_SHIFT);
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__raw_writel(v, CM_REG(CLKSEL5_PLL));
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v = __raw_readl(CM_REG(CLKEN2_PLL));
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v |= (7 << OMAP3430ES2_PERIPH2_DPLL_FREQSEL_SHIFT);
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v |= (7 << OMAP3430ES2_EN_PERIPH2_DPLL_SHIFT);
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__raw_writel(v, CM_REG(CLKEN2_PLL));
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/* PRCM settings for USBHOST:
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* Interface clk un-related to domain transition
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*/
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v = __raw_readl(CM_REG(AIDLE_USBH));
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v |= (0 << OMAP3430ES2_AUTO_USBHOST_SHIFT);
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__raw_writel(v, CM_REG(AIDLE_USBH));
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/* Disable sleep dependency with MPU and IVA */
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v = __raw_readl(CM_REG(SLEEPD_USBH));
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v |= (0 << OMAP3430ES2_EN_MPU_SHIFT);
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v |= (0 << OMAP3430ES2_EN_IVA2_SHIFT);
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__raw_writel(v, CM_REG(SLEEPD_USBH));
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/* Disable Automatic transition of clock */
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v = __raw_readl(CM_REG(CLKSTCTRL_USBH));
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v |= (0 << OMAP3430ES2_CLKTRCTRL_USBHOST_SHIFT);
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__raw_writel(v, CM_REG(CLKSTCTRL_USBH));
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/* Enable Clocks for USBHOST */
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/* enable usbhost_ick */
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v = __raw_readl(CM_REG(ICLKEN_USBH));
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v |= (1 << OMAP3430ES2_EN_USBHOST_SHIFT);
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__raw_writel(v, CM_REG(ICLKEN_USBH));
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/* enable usbhost_120m_fck */
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v = __raw_readl(CM_REG(FCLKEN_USBH));
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v |= (1 << OMAP3430ES2_EN_USBHOST2_SHIFT);
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__raw_writel(v, CM_REG(FCLKEN_USBH));
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/* enable usbhost_48m_fck */
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v = __raw_readl(CM_REG(FCLKEN_USBH));
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v |= (1 << OMAP3430ES2_EN_USBHOST1_SHIFT);
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__raw_writel(v, CM_REG(FCLKEN_USBH));
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if (omap->phy_reset) {
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/* Refer: ISSUE1 */
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if (omap->reset_gpio_port[0] != -EINVAL) {
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gpio_direction_output(omap->reset_gpio_port[0], 0);
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}
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if (omap->reset_gpio_port[1] != -EINVAL) {
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gpio_direction_output(omap->reset_gpio_port[1], 0);
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}
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/* Hold the PHY in RESET for enough time till DIR is high */
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mdelay(10);
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}
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/* enable usbtll_fck */
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v = __raw_readl(CM_REG(FCLKEN3_CORE));
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v |= (1 << OMAP3430ES2_EN_USBTLL_SHIFT);
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__raw_writel(v, CM_REG(FCLKEN3_CORE));
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/* Configure TLL for 60Mhz clk for ULPI */
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/* enable usbtll_ick */
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v = __raw_readl(CM_REG(ICLKEN3_CORE));
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v |= (1 << OMAP3430ES2_EN_USBTLL_SHIFT);
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__raw_writel(v, CM_REG(ICLKEN3_CORE));
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v = __raw_readl(CM_REG(AIDLE3_CORE));
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v |= (0 << OMAP3430ES2_AUTO_USBTLL_SHIFT);
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__raw_writel(v, CM_REG(AIDLE3_CORE));
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/* perform TLL soft reset, and wait until reset is complete */
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__raw_writel(OMAP_USBTLL_SYSCONFIG_SOFTRESET,
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OMAP_USBTLL_BASE + OMAP_USBTLL_SYSCONFIG);
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/* Wait for TLL reset to complete */
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start = get_time_ns();
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while (!(__raw_readl(OMAP_USBTLL_BASE + OMAP_USBTLL_SYSSTATUS)
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& OMAP_USBTLL_SYSSTATUS_RESETDONE)) {
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if (is_timeout(start, timeout * USECOND)) {
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return -ETIMEDOUT;
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}
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}
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/* (1<<3) = no idle mode only for initial debugging */
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__raw_writel(OMAP_USBTLL_SYSCONFIG_ENAWAKEUP |
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OMAP_USBTLL_SYSCONFIG_SIDLEMODE |
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OMAP_USBTLL_SYSCONFIG_CACTIVITY, OMAP_USBTLL_BASE + OMAP_USBTLL_SYSCONFIG);
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/* Put UHH in NoIdle/NoStandby mode */
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v = __raw_readl(OMAP_UHH_CONFIG_BASE + OMAP_UHH_SYSCONFIG);
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v |= (OMAP_UHH_SYSCONFIG_ENAWAKEUP
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| OMAP_UHH_SYSCONFIG_SIDLEMODE
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| OMAP_UHH_SYSCONFIG_CACTIVITY
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| OMAP_UHH_SYSCONFIG_MIDLEMODE);
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v &= ~OMAP_UHH_SYSCONFIG_AUTOIDLE;
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__raw_writel(v, OMAP_UHH_CONFIG_BASE + OMAP_UHH_SYSCONFIG);
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v = __raw_readl(OMAP_UHH_CONFIG_BASE + OMAP_UHH_HOSTCONFIG);
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/* setup ULPI bypass and burst configurations */
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v |= (OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN
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| OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN
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| OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN);
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v &= ~OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN;
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if (omap->port_mode[0] == EHCI_HCD_OMAP_MODE_UNKNOWN)
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v &= ~OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS;
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if (omap->port_mode[1] == EHCI_HCD_OMAP_MODE_UNKNOWN)
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v &= ~OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS;
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if (omap->port_mode[2] == EHCI_HCD_OMAP_MODE_UNKNOWN)
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v &= ~OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS;
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/* Bypass the TLL module for PHY mode operation */
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if (get_cpu_rev() <= OMAP34XX_ES2_1) {
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if ((omap->port_mode[0] == EHCI_HCD_OMAP_MODE_PHY) ||
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(omap->port_mode[1] == EHCI_HCD_OMAP_MODE_PHY) ||
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(omap->port_mode[2] == EHCI_HCD_OMAP_MODE_PHY))
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v &= ~OMAP_UHH_HOSTCONFIG_ULPI_BYPASS;
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else
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v |= OMAP_UHH_HOSTCONFIG_ULPI_BYPASS;
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} else {
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if (omap->port_mode[0] == EHCI_HCD_OMAP_MODE_PHY)
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v &= ~OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS;
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else if (omap->port_mode[0] == EHCI_HCD_OMAP_MODE_TLL)
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v |= OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS;
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if (omap->port_mode[1] == EHCI_HCD_OMAP_MODE_PHY)
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v &= ~OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS;
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else if (omap->port_mode[1] == EHCI_HCD_OMAP_MODE_TLL)
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v |= OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS;
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if (omap->port_mode[2] == EHCI_HCD_OMAP_MODE_PHY)
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v &= ~OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS;
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else if (omap->port_mode[2] == EHCI_HCD_OMAP_MODE_TLL)
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v |= OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS;
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}
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__raw_writel(v, OMAP_UHH_CONFIG_BASE + OMAP_UHH_HOSTCONFIG);
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if ((omap->port_mode[0] == EHCI_HCD_OMAP_MODE_TLL) ||
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(omap->port_mode[1] == EHCI_HCD_OMAP_MODE_TLL) ||
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(omap->port_mode[2] == EHCI_HCD_OMAP_MODE_TLL)) {
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if (omap->port_mode[0] == EHCI_HCD_OMAP_MODE_TLL)
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tll_ch_mask |= OMAP_TLL_CHANNEL_1_EN_MASK;
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if (omap->port_mode[1] == EHCI_HCD_OMAP_MODE_TLL)
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tll_ch_mask |= OMAP_TLL_CHANNEL_2_EN_MASK;
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if (omap->port_mode[2] == EHCI_HCD_OMAP_MODE_TLL)
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tll_ch_mask |= OMAP_TLL_CHANNEL_3_EN_MASK;
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/* Enable UTMI mode for required TLL channels */
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omap_usb_utmi_init(omap, tll_ch_mask);
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}
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if (omap->phy_reset) {
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/* Refer ISSUE1:
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* Hold the PHY in RESET for enough time till
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* PHY is settled and ready
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*/
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udelay(10);
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if (omap->reset_gpio_port[0] != -EINVAL)
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gpio_direction_output(omap->reset_gpio_port[0], 1);
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if (omap->reset_gpio_port[1] != -EINVAL)
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gpio_direction_output(omap->reset_gpio_port[1], 1);
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}
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return 0;
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}
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