216 lines
5.0 KiB
C
216 lines
5.0 KiB
C
#include <common.h>
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#include <linux/sizes.h>
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#include <io.h>
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#include <init.h>
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#include <asm/barebox-arm-head.h>
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#include <asm/barebox-arm.h>
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#include <mach/am33xx-silicon.h>
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#include <mach/am33xx-clock.h>
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#include <mach/generic.h>
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#include <mach/sdrc.h>
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#include <mach/sys_info.h>
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#include <mach/syslib.h>
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#include <mach/am33xx-mux.h>
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#include <mach/am33xx-generic.h>
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#include <mach/wdt.h>
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#include <debug_ll.h>
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static const struct am33xx_cmd_control pcm051_cmd = {
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.slave_ratio0 = 0x80,
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.dll_lock_diff0 = 0x0,
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.invert_clkout0 = 0x0,
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.slave_ratio1 = 0x80,
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.dll_lock_diff1 = 0x0,
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.invert_clkout1 = 0x0,
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.slave_ratio2 = 0x80,
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.dll_lock_diff2 = 0x0,
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.invert_clkout2 = 0x0,
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};
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struct pcm051_sdram_timings {
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struct am33xx_emif_regs regs;
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struct am33xx_ddr_data data;
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};
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enum {
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MT41J128M16125IT_256MB,
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MT41J64M1615IT_128MB,
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MT41J256M16HA15EIT_512MB,
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MT41J512M8125IT_2x512MB,
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};
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struct pcm051_sdram_timings timings[] = {
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/* 256MB */
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[MT41J128M16125IT_256MB] = {
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.regs = {
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.emif_read_latency = 0x7,
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.emif_tim1 = 0x0AAAD4DB,
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.emif_tim2 = 0x26437FDA,
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.emif_tim3 = 0x501F83FF,
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.sdram_config = 0x61C052B2,
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.zq_config = 0x50074BE4,
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.sdram_ref_ctrl = 0x00000C30,
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},
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.data = {
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.rd_slave_ratio0 = 0x3B,
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.wr_dqs_slave_ratio0 = 0x33,
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.fifo_we_slave_ratio0 = 0x9c,
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.wr_slave_ratio0 = 0x6f,
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},
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},
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/* 128MB */
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[MT41J64M1615IT_128MB] = {
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.regs = {
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.emif_read_latency = 0x7,
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.emif_tim1 = 0x0AAAE4DB,
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.emif_tim2 = 0x262F7FDA,
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.emif_tim3 = 0x501F82BF,
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.sdram_config = 0x61C05232,
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.zq_config = 0x50074BE4,
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.sdram_ref_ctrl = 0x00000C30,
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},
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.data = {
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.rd_slave_ratio0 = 0x38,
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.wr_dqs_slave_ratio0 = 0x34,
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.fifo_we_slave_ratio0 = 0xA2,
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.wr_slave_ratio0 = 0x72,
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},
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},
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/* 512MB */
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[MT41J256M16HA15EIT_512MB] = {
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.regs = {
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.emif_read_latency = 0x7,
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.emif_tim1 = 0x0AAAE4DB,
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.emif_tim2 = 0x266B7FDA,
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.emif_tim3 = 0x501F867F,
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.sdram_config = 0x61C05332,
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.zq_config = 0x50074BE4,
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.sdram_ref_ctrl = 0x00000C30
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},
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.data = {
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.rd_slave_ratio0 = 0x35,
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.wr_dqs_slave_ratio0 = 0x43,
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.fifo_we_slave_ratio0 = 0x97,
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.wr_slave_ratio0 = 0x7b,
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},
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},
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/* 1024MB */
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[MT41J512M8125IT_2x512MB] = {
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.regs = {
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.emif_read_latency = 0x7,
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.emif_tim1 = 0x0AAAE4DB,
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.emif_tim2 = 0x266B7FDA,
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.emif_tim3 = 0x501F867F,
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.sdram_config = 0x61C053B2,
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.zq_config = 0x50074BE4,
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.sdram_ref_ctrl = 0x00000C30
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},
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.data = {
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.rd_slave_ratio0 = 0x32,
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.wr_dqs_slave_ratio0 = 0x48,
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.fifo_we_slave_ratio0 = 0x99,
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.wr_slave_ratio0 = 0x80,
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},
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},
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};
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extern char __dtb_am335x_phytec_phycore_som_start[];
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extern char __dtb_am335x_phytec_phycore_som_mlo_start[];
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extern char __dtb_am335x_phytec_phycore_som_no_spi_start[];
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/**
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* @brief The basic entry point for board initialization.
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*
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* This is called as part of machine init (after arch init).
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* This is again called with stack in SRAM, so not too many
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* constructs possible here.
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*
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* @return void
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*/
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static noinline void pcm051_board_init(int sdram)
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{
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void *fdt;
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struct pcm051_sdram_timings *timing = &timings[sdram];
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/* WDT1 is already running when the bootloader gets control
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* Disable it to avoid "random" resets
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*/
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writel(WDT_DISABLE_CODE1, AM33XX_WDT_REG(WSPR));
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while (readl(AM33XX_WDT_REG(WWPS)) != 0x0);
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writel(WDT_DISABLE_CODE2, AM33XX_WDT_REG(WSPR));
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while (readl(AM33XX_WDT_REG(WWPS)) != 0x0);
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am33xx_pll_init(MPUPLL_M_600, 25, DDRPLL_M_400);
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am335x_sdram_init(0x18B, &pcm051_cmd,
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&timing->regs,
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&timing->data);
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am33xx_uart_soft_reset((void *)AM33XX_UART0_BASE);
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am33xx_enable_uart0_pin_mux();
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omap_uart_lowlevel_init((void *)AM33XX_UART0_BASE);
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putc_ll('>');
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fdt = __dtb_am335x_phytec_phycore_som_mlo_start - get_runtime_offset();
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am335x_barebox_entry(fdt);
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}
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static noinline void pcm051_board_entry(unsigned long bootinfo, int sdram)
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{
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am33xx_save_bootinfo((void *)bootinfo);
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arm_cpu_lowlevel_init();
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/*
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* Setup C environment, the board init code uses global variables.
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* Stackpointer has already been initialized by the ROM code.
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*/
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relocate_to_current_adr();
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setup_c();
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pcm051_board_init(sdram);
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}
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ENTRY_FUNCTION(start_am33xx_phytec_phycore_sram_256mb, bootinfo, r1, r2)
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{
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pcm051_board_entry(bootinfo, MT41J128M16125IT_256MB);
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}
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ENTRY_FUNCTION(start_am33xx_phytec_phycore_sram_128mb, bootinfo, r1, r2)
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{
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pcm051_board_entry(bootinfo, MT41J64M1615IT_128MB);
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}
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ENTRY_FUNCTION(start_am33xx_phytec_phycore_sram_512mb, bootinfo, r1, r2)
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{
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pcm051_board_entry(bootinfo, MT41J256M16HA15EIT_512MB);
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}
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ENTRY_FUNCTION(start_am33xx_phytec_phycore_sram_2x512mb, bootinfo, r1, r2)
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{
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pcm051_board_entry(bootinfo, MT41J512M8125IT_2x512MB);
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}
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ENTRY_FUNCTION(start_am33xx_phytec_phycore_sdram, r0, r1, r2)
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{
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void *fdt;
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fdt = __dtb_am335x_phytec_phycore_som_start - get_runtime_offset();
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am335x_barebox_entry(fdt);
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}
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ENTRY_FUNCTION(start_am33xx_phytec_phycore_no_spi_sdram, r0, r1, r2)
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{
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void *fdt;
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fdt = __dtb_am335x_phytec_phycore_som_no_spi_start - get_runtime_offset();
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am335x_barebox_entry(fdt);
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}
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