371 lines
8.1 KiB
C
371 lines
8.1 KiB
C
/*
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* Copyright (C) 2009 Eric Benard, Eukrea Electromatique
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* Based on pcm038.c which is :
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* Copyright (C) 2007 Sascha Hauer, Pengutronix
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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#include <common.h>
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#include <errno.h>
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#include <net.h>
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#include <init.h>
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#include <environment.h>
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#include <mach/imx-regs.h>
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#include <fec.h>
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#include <notifier.h>
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#include <mach/gpio.h>
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#include <asm/armlinux.h>
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#include <asm/mach-types.h>
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#include <mach/pmic.h>
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#include <partition.h>
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#include <fs.h>
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#include <fcntl.h>
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#include <nand.h>
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#include <command.h>
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#include <asm/io.h>
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#include <mach/imx-nand.h>
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#include <mach/imx-pll.h>
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#include <mach/imxfb.h>
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#include <ns16550.h>
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#include <asm/mmu.h>
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#include <i2c/i2c.h>
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#include <i2c/lp3972.h>
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#include <mach/iomux-mx27.h>
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static struct device_d cfi_dev = {
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.name = "cfi_flash",
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.map_base = 0xC0000000,
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.size = 32 * 1024 * 1024,
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};
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#ifdef CONFIG_EUKREA_CPUIMX27_NOR_64MB
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static struct device_d cfi_dev1 = {
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.name = "cfi_flash",
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.map_base = 0xC2000000,
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.size = 32 * 1024 * 1024,
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};
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#endif
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static struct memory_platform_data ram_pdata = {
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.name = "ram0",
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.flags = DEVFS_RDWR,
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};
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#if defined CONFIG_EUKREA_CPUIMX27_SDRAM_256MB
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#define SDRAM0 256
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#elif defined CONFIG_EUKREA_CPUIMX27_SDRAM_128MB
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#define SDRAM0 128
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#endif
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static struct device_d sdram_dev = {
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.name = "mem",
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.map_base = 0xa0000000,
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.size = SDRAM0 * 1024 * 1024,
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.platform_data = &ram_pdata,
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};
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static struct fec_platform_data fec_info = {
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.xcv_type = MII100,
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.phy_addr = 1,
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};
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static struct device_d fec_dev = {
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.name = "fec_imx",
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.map_base = 0x1002b000,
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.platform_data = &fec_info,
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};
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struct imx_nand_platform_data nand_info = {
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.width = 1,
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.hw_ecc = 1,
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.flash_bbt = 1,
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};
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static struct device_d nand_dev = {
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.name = "imx_nand",
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.map_base = 0xd8000000,
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.platform_data = &nand_info,
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};
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#ifdef CONFIG_DRIVER_SERIAL_NS16550
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unsigned int quad_uart_read(unsigned long base, unsigned char reg_idx)
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{
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unsigned int reg_addr = (unsigned int)base;
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reg_addr += reg_idx << 1;
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return 0xff & readw(reg_addr);
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}
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EXPORT_SYMBOL(quad_uart_read);
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void quad_uart_write(unsigned int val, unsigned long base,
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unsigned char reg_idx)
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{
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unsigned int reg_addr = (unsigned int)base;
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reg_addr += reg_idx << 1;
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writew(0xff & val, reg_addr);
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}
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EXPORT_SYMBOL(quad_uart_write);
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static struct NS16550_plat quad_uart_serial_plat = {
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.clock = 14745600,
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.f_caps = CONSOLE_STDIN | CONSOLE_STDOUT | CONSOLE_STDERR,
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.reg_read = quad_uart_read,
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.reg_write = quad_uart_write,
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};
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#ifdef CONFIG_EUKREA_CPUIMX27_QUART1
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#define QUART_OFFSET 0x200000
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#elif defined CONFIG_EUKREA_CPUIMX27_QUART2
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#define QUART_OFFSET 0x400000
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#elif defined CONFIG_EUKREA_CPUIMX27_QUART3
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#define QUART_OFFSET 0x800000
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#elif defined CONFIG_EUKREA_CPUIMX27_QUART4
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#define QUART_OFFSET 0x1000000
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#endif
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static struct device_d quad_uart_serial_device = {
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.name = "serial_ns16550",
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.map_base = IMX_CS3_BASE + QUART_OFFSET,
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.size = 0xF,
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.platform_data = (void *)&quad_uart_serial_plat,
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};
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#endif
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static struct i2c_board_info i2c_devices[] = {
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{
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I2C_BOARD_INFO("lp3972", 0x34),
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},
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};
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static struct device_d i2c_dev = {
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.name = "i2c-imx",
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.map_base = IMX_I2C1_BASE,
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};
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#ifdef CONFIG_MMU
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static void eukrea_cpuimx27_mmu_init(void)
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{
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mmu_init();
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arm_create_section(0xa0000000, 0xa0000000, 128, PMD_SECT_DEF_CACHED);
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arm_create_section(0xb0000000, 0xa0000000, 128, PMD_SECT_DEF_UNCACHED);
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setup_dma_coherent(0x10000000);
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#if TEXT_BASE & (0x100000 - 1)
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#warning cannot create vector section. Adjust TEXT_BASE to a 1M boundary
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#else
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arm_create_section(0x0, TEXT_BASE, 1, PMD_SECT_DEF_UNCACHED);
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#endif
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mmu_enable();
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}
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#else
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static void eukrea_cpuimx27_mmu_init(void)
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{
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}
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#endif
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#ifdef CONFIG_DRIVER_VIDEO_IMX
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static struct imx_fb_videomode imxfb_mode = {
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.mode = {
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.name = "CMO-QVGA",
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.refresh = 60,
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.xres = 320,
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.yres = 240,
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.pixclock = 156000,
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.hsync_len = 30,
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.left_margin = 38,
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.right_margin = 20,
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.vsync_len = 3,
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.upper_margin = 15,
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.lower_margin = 4,
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},
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.pcr = 0xFAD08B80,
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.bpp = 16,};
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static struct imx_fb_platform_data eukrea_cpuimx27_fb_data = {
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.mode = &imxfb_mode,
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.pwmr = 0x00A903FF,
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.lscr1 = 0x00120300,
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.dmacr = 0x00020010,
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};
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static struct device_d imxfb_dev = {
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.name = "imxfb",
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.map_base = 0x10021000,
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.size = 0x1000,
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.platform_data = &eukrea_cpuimx27_fb_data,
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};
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#endif
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static int eukrea_cpuimx27_devices_init(void)
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{
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char *envdev = "no";
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int i;
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unsigned int mode[] = {
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PD0_AIN_FEC_TXD0,
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PD1_AIN_FEC_TXD1,
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PD2_AIN_FEC_TXD2,
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PD3_AIN_FEC_TXD3,
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PD4_AOUT_FEC_RX_ER,
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PD5_AOUT_FEC_RXD1,
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PD6_AOUT_FEC_RXD2,
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PD7_AOUT_FEC_RXD3,
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PD8_AF_FEC_MDIO,
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PD9_AIN_FEC_MDC | GPIO_PUEN,
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PD10_AOUT_FEC_CRS,
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PD11_AOUT_FEC_TX_CLK,
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PD12_AOUT_FEC_RXD0,
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PD13_AOUT_FEC_RX_DV,
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PD14_AOUT_FEC_RX_CLK,
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PD15_AOUT_FEC_COL,
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PD16_AIN_FEC_TX_ER,
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PF23_AIN_FEC_TX_EN,
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PD17_PF_I2C_DATA,
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PD18_PF_I2C_CLK,
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#ifdef CONFIG_DRIVER_SERIAL_IMX
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PE12_PF_UART1_TXD,
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PE13_PF_UART1_RXD,
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PE14_PF_UART1_CTS,
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PE15_PF_UART1_RTS,
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#endif
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#ifdef CONFIG_DRIVER_VIDEO_IMX
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PA5_PF_LSCLK,
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PA6_PF_LD0,
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PA7_PF_LD1,
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PA8_PF_LD2,
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PA9_PF_LD3,
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PA10_PF_LD4,
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PA11_PF_LD5,
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PA12_PF_LD6,
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PA13_PF_LD7,
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PA14_PF_LD8,
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PA15_PF_LD9,
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PA16_PF_LD10,
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PA17_PF_LD11,
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PA18_PF_LD12,
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PA19_PF_LD13,
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PA20_PF_LD14,
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PA21_PF_LD15,
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PA22_PF_LD16,
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PA23_PF_LD17,
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PA28_PF_HSYNC,
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PA29_PF_VSYNC,
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PA31_PF_OE_ACD,
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GPIO_PORTE | 5 | GPIO_GPIO | GPIO_OUT,
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#endif
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};
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eukrea_cpuimx27_mmu_init();
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/* configure 16 bit nor flash on cs0 */
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CS0U = 0x00008F03;
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CS0L = 0xA0330D01;
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CS0A = 0x002208C0;
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/* initialize gpios */
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for (i = 0; i < ARRAY_SIZE(mode); i++)
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imx_gpio_mode(mode[i]);
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register_device(&cfi_dev);
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#ifdef CONFIG_EUKREA_CPUIMX27_NOR_64MB
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register_device(&cfi_dev1);
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#endif
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register_device(&nand_dev);
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register_device(&sdram_dev);
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PCCR0 |= PCCR0_I2C1_EN;
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i2c_register_board_info(0, i2c_devices, ARRAY_SIZE(i2c_devices));
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register_device(&i2c_dev);
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devfs_add_partition("nor0", 0x00000, 0x40000, PARTITION_FIXED, "self0");
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devfs_add_partition("nor0", 0x40000, 0x20000, PARTITION_FIXED, "env0");
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protect_file("/dev/env0", 1);
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envdev = "NOR";
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printf("Using environment in %s Flash\n", envdev);
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#ifdef CONFIG_DRIVER_VIDEO_IMX
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register_device(&imxfb_dev);
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gpio_direction_output(GPIO_PORTE | 5, 0);
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gpio_set_value(GPIO_PORTE | 5, 1);
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#endif
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armlinux_add_dram(&sdram_dev);
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armlinux_set_bootparams((void *)0xa0000100);
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armlinux_set_architecture(MACH_TYPE_CPUIMX27);
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return 0;
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}
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device_initcall(eukrea_cpuimx27_devices_init);
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#ifdef CONFIG_DRIVER_SERIAL_IMX
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static struct device_d eukrea_cpuimx27_serial_device = {
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.name = "imx_serial",
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.map_base = IMX_UART1_BASE,
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.size = 4096,
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};
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#endif
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static int eukrea_cpuimx27_console_init(void)
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{
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#ifdef CONFIG_DRIVER_SERIAL_IMX
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register_device(&eukrea_cpuimx27_serial_device);
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#endif
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/* configure 8 bit UART on cs3 */
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FMCR &= ~0x2;
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CS3U = 0x0000D603;
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CS3L = 0x0D1D0D01;
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CS3A = 0x00D20000;
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#ifdef CONFIG_DRIVER_SERIAL_NS16550
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register_device(&quad_uart_serial_device);
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#endif
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return 0;
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}
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console_initcall(eukrea_cpuimx27_console_init);
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static int eukrea_cpuimx27_late_init(void)
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{
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#ifdef CONFIG_DRIVER_I2C_LP3972
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struct i2c_client *client;
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u8 reg[1];
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#endif
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console_flush();
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register_device(&fec_dev);
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#ifdef CONFIG_DRIVER_I2C_LP3972
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client = lp3972_get_client();
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if (!client)
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return -ENODEV;
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reg[0] = 0xa0;
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i2c_write_reg(client, 0x39, reg, sizeof(reg));
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#endif
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return 0;
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}
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late_initcall(eukrea_cpuimx27_late_init);
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#ifdef CONFIG_NAND_IMX_BOOT
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void __bare_init nand_boot(void)
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{
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imx_nand_load_image((void *)TEXT_BASE, 256 * 1024);
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}
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#endif
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