142 lines
3.3 KiB
ArmAsm
142 lines
3.3 KiB
ArmAsm
#include <config.h>
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#include <mach/imx-regs.h>
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#define writel(val, reg) \
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ldr r0, =reg; \
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ldr r1, =val; \
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str r1, [r0];
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#if defined CONFIG_EUKREA_CPUIMX27_SDRAM_256MB
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#define ROWS0 ESDCTL_ROW14
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#define CFG0 0x0029572D
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#elif defined CONFIG_EUKREA_CPUIMX27_SDRAM_128MB
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#define ROWS0 ESDCTL_ROW13
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#define CFG0 0x00095728
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#endif
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#define ESDCTL0_VAL (ESDCTL0_SDE | ROWS0 | ESDCTL0_COL10)
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.macro sdram_init
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/*
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* DDR on CSD0
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*/
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writel(0x0000000C, ESDMISC) /* Enable DDR SDRAM operation */
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writel(0x55555555, DSCR(3)) /* Set the driving strength */
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writel(0x55555555, DSCR(5))
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writel(0x55555555, DSCR(6))
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writel(0x00005005, DSCR(7))
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writel(0x15555555, DSCR(8))
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writel(0x00000004, ESDMISC) /* Initial reset */
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writel(CFG0, ESDCFG0)
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writel(ESDCTL0_VAL | ESDCTL0_SMODE_PRECHARGE, ESDCTL0) /* precharge CSD0 all banks */
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writel(0x00000000, 0xA0000F00) /* CSD0 precharge address (A10 = 1) */
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writel(ESDCTL0_VAL | ESDCTL0_SMODE_AUTO_REFRESH, ESDCTL0)
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ldr r0, =0xa0000f00
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mov r1, #0
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mov r2, #8
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1:
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str r1, [r0]
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subs r2, #1
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bne 1b
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writel(ESDCTL0_VAL | ESDCTL0_SMODE_LOAD_MODE, ESDCTL0)
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ldr r0, =0xA0000033
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mov r1, #0xda
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strb r1, [r0]
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#if defined CONFIG_EUKREA_CPUIMX27_SDRAM_256MB
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ldr r0, =0xA2000000
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#elif defined CONFIG_EUKREA_CPUIMX27_SDRAM_128MB
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ldr r0, =0xA1000000
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#endif
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mov r1, #0xff
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strb r1, [r0]
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writel(ESDCTL0_VAL | ESDCTL0_DSIZ_31_0 | ESDCTL0_REF4 | ESDCTL0_BL | ESDCTL0_SMODE_NORMAL, ESDCTL0)
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.endm
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.section ".text_bare_init","ax"
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.globl board_init_lowlevel
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board_init_lowlevel:
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mov r10, lr
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/* ahb lite ip interface */
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writel(0x20040304, AIPI1_PSR0)
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writel(0xDFFBFCFB, AIPI1_PSR1)
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writel(0x00000000, AIPI2_PSR0)
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writel(0xFFFFFFFF, AIPI2_PSR1)
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/* disable mpll/spll */
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ldr r0, =CSCR
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ldr r1, [r0]
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bic r1, r1, #0x03
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str r1, [r0]
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/*
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* pll clock initialization - see section 3.4.3 of the i.MX27 manual
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*/
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writel(0x00331C23, MPCTL0) /* MPLL = 399 MHz */
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writel(0x040C2403, SPCTL0) /* SPLL = 240 MHz */
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writel(0x33F38107 | CSCR_MPLL_RESTART | CSCR_SPLL_RESTART, CSCR)
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/* add some delay here */
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mov r1, #0x1000
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1: subs r1, r1, #0x1
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bne 1b
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/* clock gating enable */
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writel(0x00050f08, GPCR)
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/* peripheral clock divider */
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writel(0x130400c3, PCDR0) /* FIXME */
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writel(0x09030208, PCDR1) /* PERDIV1=08 @133 MHz */
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/* PERDIV1=04 @266 MHz */
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/* skip sdram initialization if we run from ram */
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cmp pc, #0xa0000000
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bls 1f
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cmp pc, #0xc0000000
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bhi 1f
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mov pc,r10
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1:
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sdram_init
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#ifdef CONFIG_NAND_IMX_BOOT
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ldr sp, =0xa0f00000 /* Setup a temporary stack in SDRAM */
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ldr r0, =IMX_NFC_BASE /* start of NFC SRAM */
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ldr r2, =IMX_NFC_BASE + 0x1000 /* end of NFC SRAM */
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/* skip NAND boot if not running from NFC space */
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cmp pc, r0
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bls ret
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cmp pc, r2
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bhi ret
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/* Move ourselves out of NFC SRAM */
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ldr r1, =TEXT_BASE
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copy_loop:
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ldmia r0!, {r3-r9} /* copy from source address [r0] */
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stmia r1!, {r3-r9} /* copy to target address [r1] */
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cmp r0, r2 /* until source end addreee [r2] */
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ble copy_loop
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ldr pc, =1f /* Jump to SDRAM */
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1:
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bl nand_boot /* Load barebox from NAND Flash */
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ldr r1, =IMX_NFC_BASE - TEXT_BASE
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sub r10, r10, r1 /* adjust return address from NFC SRAM */
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/* to SDRAM */
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#endif /* CONFIG_NAND_IMX_BOOT */
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ret:
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mov pc,r10
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