128 lines
3.2 KiB
C
128 lines
3.2 KiB
C
/*
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* Copyright (C) 2012 Alexander Shiyan <shc_work@mail.ru>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*/
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#include <common.h>
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#include <init.h>
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#include <sizes.h>
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#include <asm/io.h>
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#include <linux/clk.h>
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#include <linux/clkdev.h>
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#include <mach/clps711x.h>
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#define CLPS711X_OSC_FREQ 3686400
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#define CLPS711X_EXT_FREQ 13000000
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enum clps711x_clks {
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dummy, cpu, bus, uart, timer_hf, timer_lf, tc1, tc2, clk_max
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};
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static struct {
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const char *name;
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struct clk *clk;
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} clks[clk_max] = {
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{ "dummy", },
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{ "cpu", },
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{ "bus", },
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{ "uart", },
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{ "timer_hf", },
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{ "timer_lf", },
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{ "tc1", },
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{ "tc2", },
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};
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static const char *tc_sel_clks[] = {
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"timer_lf",
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"timer_hf",
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};
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static __init void clps711x_clk_register(enum clps711x_clks id)
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{
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clk_register_clkdev(clks[id].clk, clks[id].name, NULL);
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}
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static __init int clps711x_clk_init(void)
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{
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unsigned int f_cpu, f_bus, f_uart, f_timer_hf, f_timer_lf, pll;
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u32 tmp;
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tmp = readl(PLLR) >> 24;
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if (tmp)
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pll = (CLPS711X_OSC_FREQ * tmp) / 2;
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else
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pll = 73728000; /* Default value for old CPUs */
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tmp = readl(SYSFLG2);
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if (tmp & SYSFLG2_CKMODE) {
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f_cpu = CLPS711X_EXT_FREQ;
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f_bus = CLPS711X_EXT_FREQ;
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} else {
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f_cpu = pll;
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if (f_cpu >= 36864000)
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f_bus = f_cpu / 2;
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else
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f_bus = 36864000 / 2;
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}
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f_uart = f_bus / 10;
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if (tmp & SYSFLG2_CKMODE) {
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tmp = readw(SYSCON2);
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if (tmp & SYSCON2_OSTB)
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f_timer_hf = DIV_ROUND_CLOSEST(CLPS711X_EXT_FREQ, 26);
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else
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f_timer_hf = DIV_ROUND_CLOSEST(CLPS711X_EXT_FREQ, 24);
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} else
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f_timer_hf = DIV_ROUND_CLOSEST(f_cpu, 144);
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f_timer_lf = DIV_ROUND_CLOSEST(f_timer_hf, 256);
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/* Turn timers in free running mode */
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tmp = readl(SYSCON1);
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tmp &= ~(SYSCON1_TC1M | SYSCON1_TC2M);
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writel(tmp, SYSCON1);
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clks[dummy].clk = clk_fixed(clks[dummy].name, 0);
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clks[cpu].clk = clk_fixed(clks[cpu].name, f_cpu);
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clks[bus].clk = clk_fixed(clks[bus].name, f_bus);
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clks[uart].clk = clk_fixed(clks[uart].name, f_uart);
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clks[timer_hf].clk = clk_fixed(clks[timer_hf].name, f_timer_hf);
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clks[timer_lf].clk = clk_fixed(clks[timer_lf].name, f_timer_lf);
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clks[tc1].clk = clk_mux(clks[tc1].name, IOMEM(SYSCON1), 5, 1,
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tc_sel_clks, ARRAY_SIZE(tc_sel_clks), 0);
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clks[tc2].clk = clk_mux(clks[tc2].name, IOMEM(SYSCON1), 7, 1,
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tc_sel_clks, ARRAY_SIZE(tc_sel_clks), 0);
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clps711x_clk_register(dummy);
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clps711x_clk_register(cpu);
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clps711x_clk_register(bus);
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clps711x_clk_register(uart);
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clps711x_clk_register(timer_hf);
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clps711x_clk_register(timer_lf);
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clps711x_clk_register(tc1);
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clps711x_clk_register(tc2);
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return 0;
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}
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postcore_initcall(clps711x_clk_init);
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static const char *clps711x_clocksrc_name = "clps711x-cs";
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static __init int clps711x_core_init(void)
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{
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/* Using TC2 in low frequency mode as clocksource */
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clk_set_parent(clks[tc2].clk, clks[timer_lf].clk);
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clk_add_alias(NULL, clps711x_clocksrc_name, "tc2", NULL);
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add_generic_device(clps711x_clocksrc_name, DEVICE_ID_SINGLE, NULL,
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TC2D, SZ_2, IORESOURCE_MEM, NULL);
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return 0;
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}
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coredevice_initcall(clps711x_core_init);
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