253 lines
7.9 KiB
C
253 lines
7.9 KiB
C
/*
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* Hardware definitions for Cirrus Logic CLPS711X
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*
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* Copyright (C) 2000 Deep Blue Solutions Ltd.
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* Copyright (C) 2012 Alexander Shiyan <shc_work@mail.ru>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef __MACH_CLPS711X_H
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#define __MACH_CLPS711X_H
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#define CS0_BASE (0x00000000)
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#define CS1_BASE (0x10000000)
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#define CS2_BASE (0x20000000)
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#define CS3_BASE (0x30000000)
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#define CS4_BASE (0x40000000)
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#define CS5_BASE (0x50000000)
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#define CS6_BASE (0x60000000)
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#define CS7_BASE (0x70000000)
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#define REGS_BASE (0x80000000)
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#define SDRAM0_BASE (0xc0000000)
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#define SDRAM1_BASE (0xd0000000)
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#define PADR (REGS_BASE + 0x0000)
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#define PBDR (REGS_BASE + 0x0001)
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#define PCDR (REGS_BASE + 0x0002)
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#define PDDR (REGS_BASE + 0x0003)
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#define PADDR (REGS_BASE + 0x0040)
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#define PBDDR (REGS_BASE + 0x0041)
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#define PCDDR (REGS_BASE + 0x0042)
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#define PDDDR (REGS_BASE + 0x0043)
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#define PEDR (REGS_BASE + 0x0083)
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#define PEDDR (REGS_BASE + 0x00c3)
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#define SYSCON1 (REGS_BASE + 0x0100)
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#define SYSFLG1 (REGS_BASE + 0x0140)
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#define MEMCFG1 (REGS_BASE + 0x0180)
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#define MEMCFG2 (REGS_BASE + 0x01c0)
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#define DRFPR (REGS_BASE + 0x0200)
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#define INTSR1 (REGS_BASE + 0x0240)
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#define INTMR1 (REGS_BASE + 0x0280)
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#define LCDCON (REGS_BASE + 0x02c0)
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#define TC1D (REGS_BASE + 0x0300)
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#define TC2D (REGS_BASE + 0x0340)
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#define RTCDR (REGS_BASE + 0x0380)
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#define RTCMR (REGS_BASE + 0x03c0)
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#define PMPCON (REGS_BASE + 0x0400)
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#define CODR (REGS_BASE + 0x0440)
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#define UARTDR1 (REGS_BASE + 0x0480)
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#define UBRLCR1 (REGS_BASE + 0x04c0)
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#define SYNCIO (REGS_BASE + 0x0500)
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#define PALLSW (REGS_BASE + 0x0540)
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#define PALMSW (REGS_BASE + 0x0580)
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#define STFCLR (REGS_BASE + 0x05c0)
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#define BLEOI (REGS_BASE + 0x0600)
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#define MCEOI (REGS_BASE + 0x0640)
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#define TEOI (REGS_BASE + 0x0680)
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#define TC1EOI (REGS_BASE + 0x06c0)
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#define TC2EOI (REGS_BASE + 0x0700)
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#define RTCEOI (REGS_BASE + 0x0740)
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#define UMSEOI (REGS_BASE + 0x0780)
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#define COEOI (REGS_BASE + 0x07c0)
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#define HALT (REGS_BASE + 0x0800)
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#define STDBY (REGS_BASE + 0x0840)
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#define FBADDR (REGS_BASE + 0x1000)
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#define SYSCON2 (REGS_BASE + 0x1100)
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#define SYSFLG2 (REGS_BASE + 0x1140)
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#define INTSR2 (REGS_BASE + 0x1240)
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#define INTMR2 (REGS_BASE + 0x1280)
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#define UARTDR2 (REGS_BASE + 0x1480)
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#define UBRLCR2 (REGS_BASE + 0x14c0)
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#define SS2DR (REGS_BASE + 0x1500)
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#define SRXEOF (REGS_BASE + 0x1600)
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#define SS2POP (REGS_BASE + 0x16c0)
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#define KBDEOI (REGS_BASE + 0x1700)
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#define DAIR (REGS_BASE + 0x2000)
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#define DAIDR0 (REGS_BASE + 0x2040)
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#define DAIDR1 (REGS_BASE + 0x2080)
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#define DAIDR2 (REGS_BASE + 0x20c0)
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#define DAISR (REGS_BASE + 0x2100)
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#define SYSCON3 (REGS_BASE + 0x2200)
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#define INTSR3 (REGS_BASE + 0x2240)
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#define INTMR3 (REGS_BASE + 0x2280)
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#define LEDFLSH (REGS_BASE + 0x22c0)
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#define SDCONF (REGS_BASE + 0x2300)
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#define SDRFPR (REGS_BASE + 0x2340)
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#define UNIQID (REGS_BASE + 0x2440)
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#define DAI64FS (REGS_BASE + 0x2600)
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#define PLLW (REGS_BASE + 0x2610)
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#define PLLR (REGS_BASE + 0xa5a8)
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#define RANDID0 (REGS_BASE + 0x2700)
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#define RANDID1 (REGS_BASE + 0x2704)
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#define RANDID2 (REGS_BASE + 0x2708)
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#define RANDID3 (REGS_BASE + 0x270c)
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#define SYSCON1_KBDSCAN(x) ((x) & 15)
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#define SYSCON1_KBDSCANMASK (15)
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#define SYSCON1_TC1M (1 << 4)
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#define SYSCON1_TC1S (1 << 5)
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#define SYSCON1_TC2M (1 << 6)
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#define SYSCON1_TC2S (1 << 7)
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#define SYSCON1_BZTOG (1 << 9)
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#define SYSCON1_BZMOD (1 << 10)
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#define SYSCON1_DBGEN (1 << 11)
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#define SYSCON1_LCDEN (1 << 12)
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#define SYSCON1_CDENTX (1 << 13)
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#define SYSCON1_CDENRX (1 << 14)
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#define SYSCON1_SIREN (1 << 15)
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#define SYSCON1_ADCKSEL(x) (((x) & 3) << 16)
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#define SYSCON1_ADCKSEL_MASK (3 << 16)
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#define SYSCON1_EXCKEN (1 << 18)
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#define SYSCON1_WAKEDIS (1 << 19)
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#define SYSCON1_IRTXM (1 << 20)
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#define SYSFLG1_MCDR (1 << 0)
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#define SYSFLG1_DCDET (1 << 1)
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#define SYSFLG1_WUDR (1 << 2)
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#define SYSFLG1_WUON (1 << 3)
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#define SYSFLG1_CTS (1 << 8)
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#define SYSFLG1_DSR (1 << 9)
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#define SYSFLG1_DCD (1 << 10)
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#define SYSFLG1_NBFLG (1 << 12)
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#define SYSFLG1_RSTFLG (1 << 13)
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#define SYSFLG1_PFFLG (1 << 14)
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#define SYSFLG1_CLDFLG (1 << 15)
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#define SYSFLG1_CRXFE (1 << 24)
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#define SYSFLG1_CTXFF (1 << 25)
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#define SYSFLG1_SSIBUSY (1 << 26)
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#define SYSFLG1_ID (1 << 29)
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#define SYSFLG1_VERID(x) (((x) >> 30) & 3)
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#define SYSFLG1_VERID_MASK (3 << 30)
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#define SYSFLG2_SSRXOF (1 << 0)
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#define SYSFLG2_RESVAL (1 << 1)
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#define SYSFLG2_RESFRM (1 << 2)
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#define SYSFLG2_SS2RXFE (1 << 3)
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#define SYSFLG2_SS2TXFF (1 << 4)
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#define SYSFLG2_SS2TXUF (1 << 5)
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#define SYSFLG2_CKMODE (1 << 6)
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#define LCDCON_GSEN (1 << 30)
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#define LCDCON_GSMD (1 << 31)
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#define SYSCON2_SERSEL (1 << 0)
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#define SYSCON2_KBD6 (1 << 1)
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#define SYSCON2_DRAMZ (1 << 2)
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#define SYSCON2_KBWEN (1 << 3)
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#define SYSCON2_SS2TXEN (1 << 4)
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#define SYSCON2_PCCARD1 (1 << 5)
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#define SYSCON2_PCCARD2 (1 << 6)
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#define SYSCON2_SS2RXEN (1 << 7)
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#define SYSCON2_SS2MAEN (1 << 9)
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#define SYSCON2_OSTB (1 << 12)
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#define SYSCON2_CLKENSL (1 << 13)
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#define SYSCON2_BUZFREQ (1 << 14)
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#define SYNCIO_FRMLEN(x) (((x) & 0x1f) << 8)
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#define SYNCIO_SMCKEN (1 << 13)
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#define SYNCIO_TXFRMEN (1 << 14)
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#define DAIR_RESERVED (0x0404)
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#define DAIR_DAIEN (1 << 16)
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#define DAIR_ECS (1 << 17)
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#define DAIR_LCTM (1 << 19)
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#define DAIR_LCRM (1 << 20)
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#define DAIR_RCTM (1 << 21)
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#define DAIR_RCRM (1 << 22)
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#define DAIR_LBM (1 << 23)
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#define DAIDR2_FIFOEN (1 << 15)
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#define DAIDR2_FIFOLEFT (0x0d << 16)
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#define DAIDR2_FIFORIGHT (0x11 << 16)
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#define DAISR_RCTS (1 << 0)
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#define DAISR_RCRS (1 << 1)
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#define DAISR_LCTS (1 << 2)
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#define DAISR_LCRS (1 << 3)
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#define DAISR_RCTU (1 << 4)
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#define DAISR_RCRO (1 << 5)
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#define DAISR_LCTU (1 << 6)
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#define DAISR_LCRO (1 << 7)
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#define DAISR_RCNF (1 << 8)
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#define DAISR_RCNE (1 << 9)
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#define DAISR_LCNF (1 << 10)
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#define DAISR_LCNE (1 << 11)
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#define DAISR_FIFO (1 << 12)
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#define DAI64FS_I2SF64 (1 << 0)
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#define DAI64FS_AUDIOCLKEN (1 << 1)
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#define DAI64FS_AUDIOCLKSRC (1 << 2)
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#define DAI64FS_MCLK256EN (1 << 3)
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#define DAI64FS_LOOPBACK (1 << 5)
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#define DAI64FS_AUDIV_MASK (0x7f)
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#define DAI64FS_AUDIV(x) (((x) & DAI64FS_AUDIV_MASK) << 8)
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#define SYSCON3_ADCCON (1 << 0)
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#define SYSCON3_CLKCTL0 (1 << 1)
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#define SYSCON3_CLKCTL1 (1 << 2)
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#define SYSCON3_DAISEL (1 << 3)
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#define SYSCON3_ADCCKNSEN (1 << 4)
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#define SYSCON3_VERSN(x) (((x) >> 5) & 7)
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#define SYSCON3_VERSN_MASK (7 << 5)
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#define SYSCON3_FASTWAKE (1 << 8)
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#define SYSCON3_DAIEN (1 << 9)
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#define SYSCON3_128FS SYSCON3_DAIEN
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#define SYSCON3_ENPD67 (1 << 10)
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#define SDCONF_ACTIVE (1 << 10)
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#define SDCONF_CLKCTL (1 << 9)
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#define SDCONF_WIDTH_4 (0 << 7)
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#define SDCONF_WIDTH_8 (1 << 7)
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#define SDCONF_WIDTH_16 (2 << 7)
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#define SDCONF_WIDTH_32 (3 << 7)
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#define SDCONF_SIZE_16 (0 << 5)
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#define SDCONF_SIZE_64 (1 << 5)
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#define SDCONF_SIZE_128 (2 << 5)
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#define SDCONF_SIZE_256 (3 << 5)
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#define SDCONF_CASLAT_2 (2)
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#define SDCONF_CASLAT_3 (3)
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#define MEMCFG_BUS_WIDTH_32 (1)
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#define MEMCFG_BUS_WIDTH_16 (0)
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#define MEMCFG_BUS_WIDTH_8 (3)
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#define MEMCFG_SQAEN (1 << 6)
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#define MEMCFG_CLKENB (1 << 7)
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#define MEMCFG_WAITSTATE_8_3 (0 << 2)
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#define MEMCFG_WAITSTATE_7_3 (1 << 2)
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#define MEMCFG_WAITSTATE_6_3 (2 << 2)
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#define MEMCFG_WAITSTATE_5_3 (3 << 2)
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#define MEMCFG_WAITSTATE_4_2 (4 << 2)
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#define MEMCFG_WAITSTATE_3_2 (5 << 2)
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#define MEMCFG_WAITSTATE_2_2 (6 << 2)
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#define MEMCFG_WAITSTATE_1_2 (7 << 2)
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#define MEMCFG_WAITSTATE_8_1 (8 << 2)
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#define MEMCFG_WAITSTATE_7_1 (9 << 2)
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#define MEMCFG_WAITSTATE_6_1 (10 << 2)
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#define MEMCFG_WAITSTATE_5_1 (11 << 2)
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#define MEMCFG_WAITSTATE_4_0 (12 << 2)
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#define MEMCFG_WAITSTATE_3_0 (13 << 2)
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#define MEMCFG_WAITSTATE_2_0 (14 << 2)
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#define MEMCFG_WAITSTATE_1_0 (15 << 2)
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void clps711x_barebox_entry(u32, void *);
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#endif
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