74 lines
1.8 KiB
C
74 lines
1.8 KiB
C
/*
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* Copyright (C) 2012 Alexander Shiyan <shc_work@mail.ru>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*/
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#include <common.h>
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#include <init.h>
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#include <sizes.h>
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#include <asm/io.h>
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#include <asm/barebox-arm.h>
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#include <asm/barebox-arm-head.h>
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#include <mach/clps711x.h>
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void __naked __bare_init clps711x_barebox_entry(u32 pllmult, void *data)
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{
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u32 cpu, bus;
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/* Check if we running from external 13 MHz clock */
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if (!(readl(SYSFLG2) & SYSFLG2_CKMODE)) {
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/* Setup bus wait state scaling factor to 2 */
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writel(SYSCON3_CLKCTL0 | SYSCON3_CLKCTL1, SYSCON3);
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asm("nop");
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/* Check valid multiplier, default to 74 MHz */
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if ((pllmult < 20) || (pllmult > 50))
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pllmult = 40;
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/* Setup PLL */
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writel(pllmult << 24, PLLW);
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asm("nop");
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/* Check for old CPUs without PLL */
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if ((readl(PLLR) >> 24) != pllmult)
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cpu = 73728000;
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else
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cpu = pllmult * 3686400;
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if (cpu >= 36864000)
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bus = cpu / 2;
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else
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bus = 36864000 / 2;
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} else {
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bus = 13000000;
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/* Setup bus wait state scaling factor to 1 */
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writel(0, SYSCON3);
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asm("nop");
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}
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/* CLKEN select, SDRAM width=32 */
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writel(SYSCON2_CLKENSL, SYSCON2);
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/* Setup SDRAM params (64MB, 16Bit*2, CAS=3) */
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writel(SDCONF_CASLAT_3 | SDCONF_SIZE_256 | SDCONF_WIDTH_16 |
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SDCONF_CLKCTL | SDCONF_ACTIVE, SDCONF);
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/* Setup Refresh Rate (64ms 8K Blocks) */
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writel((64 * bus) / (8192 * 1000), SDRFPR);
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/* Disable UART, IrDa, LCD */
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writel(0, SYSCON1);
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/* Disable PWM */
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writew(0, PMPCON);
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/* Disable LED flasher */
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writew(0, LEDFLSH);
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barebox_arm_entry(SDRAM0_BASE, SZ_8M, data);
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}
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