70 lines
2.4 KiB
C
70 lines
2.4 KiB
C
/*
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* Copyright 2013 GE Intelligent Platforms, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <common.h>
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#include <mach/mmu.h>
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struct fsl_e_tlb_entry tlb_table[] = {
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/* TLB 0 - for temp stack in cache */
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FSL_SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR,
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MAS3_SX | MAS3_SW | MAS3_SR, 0,
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0, 0, BOOKE_PAGESZ_4K, 0),
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FSL_SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + (4 * 1024),
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CFG_INIT_RAM_ADDR + (4 * 1024),
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MAS3_SX | MAS3_SW | MAS3_SR, 0,
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0, 0, BOOKE_PAGESZ_4K, 0),
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FSL_SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + (8 * 1024),
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CFG_INIT_RAM_ADDR + (8 * 1024),
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MAS3_SX | MAS3_SW | MAS3_SR, 0,
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0, 0, BOOKE_PAGESZ_4K, 0),
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FSL_SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + (12 * 1024),
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CFG_INIT_RAM_ADDR + (12 * 1024),
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MAS3_SX | MAS3_SW | MAS3_SR, 0,
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0, 0, BOOKE_PAGESZ_4K, 0),
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/*
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* TLB 0/1: 2x16M Cache inhibited, guarded
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* CPLD and NAND in cache-inhibited area.
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*/
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FSL_SET_TLB_ENTRY(1, BOOT_BLOCK, BOOT_BLOCK,
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MAS3_SX | MAS3_SW | MAS3_SR,
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MAS2_W | MAS2_I | MAS2_G | MAS2_M,
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0, 0, BOOKE_PAGESZ_16M, 1),
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FSL_SET_TLB_ENTRY(1, BOOT_BLOCK + 0x1000000,
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BOOT_BLOCK + 0x1000000,
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MAS3_SX | MAS3_SW | MAS3_SR,
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MAS2_W | MAS2_I | MAS2_G | MAS2_M,
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0, 1, BOOKE_PAGESZ_16M, 1),
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/*
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* The boot flash is mapped with the cache enabled.
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* TLB 2/3: 2x16M Cacheable Write-through, guarded
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*/
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FSL_SET_TLB_ENTRY(1, BOOT_BLOCK + (2 * 0x1000000),
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BOOT_BLOCK + (2 * 0x1000000),
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MAS3_SX | MAS3_SW | MAS3_SR,
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MAS2_W | MAS2_G | MAS2_M,
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0, 2, BOOKE_PAGESZ_16M, 1),
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FSL_SET_TLB_ENTRY(1, BOOT_BLOCK + (3 * 0x1000000),
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BOOT_BLOCK + (3 * 0x1000000),
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MAS3_SX | MAS3_SW | MAS3_SR,
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MAS2_W | MAS2_G | MAS2_M,
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0, 3, BOOKE_PAGESZ_16M, 1),
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FSL_SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS,
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MAS3_SX | MAS3_SW | MAS3_SR,
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MAS2_I | MAS2_G,
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0, 4, BOOKE_PAGESZ_64M, 1),
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};
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int num_tlb_entries = ARRAY_SIZE(tlb_table);
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