79 lines
5.0 KiB
C
79 lines
5.0 KiB
C
/*
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* Copyright (C) 2003 Arabella Software Ltd.
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* Yuli Barcohen <yuli@arabellasw.com>
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*
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* Serial Presence Detect (SPD) EEPROM format according to the
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* Intel's PC SDRAM Serial Presence Detect (SPD) Specification,
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* revision 1.2B, November 1999
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#ifndef _SPD_H_
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#define _SPD_H_
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typedef struct spd_eeprom_s {
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unsigned char info_size; /* # of bytes written into serial memory */
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unsigned char chip_size; /* Total # of bytes of SPD memory device */
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unsigned char mem_type; /* Fundamental memory type (FPM, EDO, SDRAM...) */
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unsigned char nrow_addr; /* # of Row Addresses on this assembly */
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unsigned char ncol_addr; /* # of Column Addresses on this assembly */
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unsigned char nrows; /* # of Module Rows on this assembly */
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unsigned char dataw_lsb; /* Data Width of this assembly */
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unsigned char dataw_msb; /* ... Data Width continuation */
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unsigned char voltage; /* Voltage interface standard of this assembly */
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unsigned char clk_cycle; /* SDRAM Cycle time at CL=X */
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unsigned char clk_access; /* SDRAM Access from Clock at CL=X */
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unsigned char config; /* DIMM Configuration type (non-parity, ECC) */
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unsigned char refresh; /* Refresh Rate/Type */
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unsigned char primw; /* Primary SDRAM Width */
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unsigned char ecw; /* Error Checking SDRAM width */
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unsigned char min_delay; /* Min Clock Delay for Back to Back Random Address */
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unsigned char burstl; /* Burst Lengths Supported */
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unsigned char nbanks; /* # of Banks on Each SDRAM Device */
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unsigned char cas_lat; /* CAS# Latencies Supported */
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unsigned char cs_lat; /* CS# Latency */
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unsigned char write_lat; /* Write Latency (also called Write Recovery time) */
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unsigned char mod_attr; /* SDRAM Module Attributes */
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unsigned char dev_attr; /* SDRAM Device Attributes */
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unsigned char clk_cycle2; /* Min SDRAM Cycle time at CL=X-1 */
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unsigned char clk_access2; /* SDRAM Access from Clock at CL=X-1 */
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unsigned char clk_cycle3; /* Min SDRAM Cycle time at CL=X-2 */
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unsigned char clk_access3; /* Max SDRAM Access from Clock at CL=X-2 */
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unsigned char trp; /* Min Row Precharge Time (tRP) */
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unsigned char trrd; /* Min Row Active to Row Active (tRRD) */
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unsigned char trcd; /* Min RAS to CAS Delay (tRCD) */
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unsigned char tras; /* Minimum RAS Pulse Width (tRAS) */
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unsigned char row_dens; /* Density of each row on module */
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unsigned char ca_setup; /* Command and Address signal input setup time */
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unsigned char ca_hold; /* Command and Address signal input hold time */
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unsigned char data_setup; /* Data signal input setup time */
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unsigned char data_hold; /* Data signal input hold time */
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unsigned char sset[26]; /* Superset Information (may be used in future) */
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unsigned char spd_rev; /* SPD Data Revision Code */
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unsigned char cksum; /* Checksum for bytes 0-62 */
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unsigned char mid[8]; /* Manufacturer's JEDEC ID code per JEP-108E */
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unsigned char mloc; /* Manufacturing Location */
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unsigned char mpart[18]; /* Manufacturer's Part Number */
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unsigned char rev[2]; /* Revision Code */
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unsigned char mdate[2]; /* Manufacturing Date */
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unsigned char sernum[4]; /* Assembly Serial Number */
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unsigned char mspec[27]; /* Manufacturer Specific Data */
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unsigned char freq; /* Intel specification frequency */
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unsigned char intel_cas; /* Intel Specification CAS# Latency support */
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} spd_eeprom_t;
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#endif /* _SPD_H_ */
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