183 lines
5.4 KiB
C
183 lines
5.4 KiB
C
#ifndef __ASM_MACH_ATH79_PBL_MACROS_H
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#define __ASM_MACH_ATH79_PBL_MACROS_H
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#include <asm/addrspace.h>
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#include <asm/regdef.h>
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#include <mach/ar71xx_regs.h>
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#define PLL_BASE (KSEG1 | AR71XX_PLL_BASE)
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#define PLL_CPU_CONFIG_REG (PLL_BASE | AR933X_PLL_CPU_CONFIG_REG)
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#define PLL_CPU_CONFIG2_REG (PLL_BASE | AR933X_PLL_CPU_CONFIG2_REG)
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#define PLL_CLOCK_CTRL_REG (PLL_BASE | AR933X_PLL_CLOCK_CTRL_REG)
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#define DEF_25MHZ_PLL_CLOCK_CTRL \
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((2 - 1) << AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT \
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| (1 - 1) << AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT \
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| (1 - 1) << AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT)
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#define DEF_25MHZ_SETTLE_TIME (34000 / 40)
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#define DEF_25MHZ_PLL_CONFIG ( 1 << AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT \
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| 1 << AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT \
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| 32 << AR933X_PLL_CPU_CONFIG_NINT_SHIFT)
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.macro pbl_ar9331_pll
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.set push
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.set noreorder
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/* Most devices have 25 MHz Ref clock. */
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pbl_reg_writel (DEF_25MHZ_PLL_CLOCK_CTRL | AR933X_PLL_CLOCK_CTRL_BYPASS), \
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PLL_CLOCK_CTRL_REG
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pbl_reg_writel DEF_25MHZ_SETTLE_TIME, PLL_CPU_CONFIG2_REG
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pbl_reg_writel (DEF_25MHZ_PLL_CONFIG | AR933X_PLL_CPU_CONFIG_PLLPWD), \
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PLL_CPU_CONFIG_REG
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/* power on CPU PLL */
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pbl_reg_clr AR933X_PLL_CPU_CONFIG_PLLPWD, PLL_CPU_CONFIG_REG
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/* disable PLL bypass */
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pbl_reg_clr AR933X_PLL_CLOCK_CTRL_BYPASS, PLL_CLOCK_CTRL_REG
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pbl_sleep t2, 40
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.set pop
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.endm
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#define DDR_BASE (KSEG1 | AR71XX_DDR_CTRL_BASE)
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#define DDR_CONFIG (DDR_BASE | AR933X_DDR_CONFIG)
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#define DDR_CONFIG2 (DDR_BASE | AR933X_DDR_CONFIG2)
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#define DDR_MODE (DDR_BASE | AR933X_DDR_MODE)
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#define DDR_EXT_MODE (DDR_BASE | AR933X_DDR_EXT_MODE)
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#define DDR_CTRL (DDR_BASE | AR933X_DDR_CTRL)
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/* Forces an EMR3S (Extended Mode Register 3 Set) update cycle */
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#define DDR_CTRL_EMR3 BIT(5)
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/* Forces an EMR2S (Extended Mode Register 2 Set) update cycle */
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#define DDR_CTRL_EMR2 BIT(4)
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#define DDR_CTRL_PREA BIT(3) /* Forces a PRECHARGE ALL cycle */
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#define DDR_CTRL_REF BIT(2) /* Forces an AUTO REFRESH cycle */
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/* Forces an EMRS (Extended Mode Register 2 Set) update cycle */
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#define DDR_CTRL_EMRS BIT(1)
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/* Forces a MRS (Mode Register Set) update cycle */
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#define DDR_CTRL_MRS BIT(0)
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#define DDR_REFRESH (DDR_BASE | AR933X_DDR_REFRESH)
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#define DDR_RD_DATA (DDR_BASE | AR933X_DDR_RD_DATA)
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#define DDR_TAP_CTRL0 (DDR_BASE | AR933X_DDR_TAP_CTRL0)
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#define DDR_TAP_CTRL1 (DDR_BASE | AR933X_DDR_TAP_CTRL1)
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#define DDR_DDR2_CONFIG (DDR_BASE | AR933X_DDR_DDR_DDR2_CONFIG)
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#define DDR_EMR2 (DDR_BASE | AR933X_DDR_DDR_EMR2)
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#define DDR_EMR3 (DDR_BASE | AR933X_DDR_DDR_EMR3)
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.macro pbl_ar9331_ddr1_config
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.set push
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.set noreorder
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pbl_reg_writel 0x7fbc8cd0, DDR_CONFIG
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pbl_reg_writel 0x9dd0e6a8, DDR_CONFIG2
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pbl_reg_writel DDR_CTRL_PREA, DDR_CTRL
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/* 0x133: on reset Mode Register value */
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pbl_reg_writel 0x133, DDR_MODE
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pbl_reg_writel DDR_CTRL_MRS, DDR_CTRL
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/*
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* DDR_EXT_MODE[1] = 1: Reduced Drive Strength
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* DDR_EXT_MODE[0] = 0: Enable DLL
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*/
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pbl_reg_writel 0x2, DDR_EXT_MODE
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pbl_reg_writel DDR_CTRL_EMRS, DDR_CTRL
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pbl_reg_writel DDR_CTRL_PREA, DDR_CTRL
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/* DLL out of reset, CAS Latency 3 */
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pbl_reg_writel 0x33, DDR_MODE
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pbl_reg_writel DDR_CTRL_MRS, DDR_CTRL
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/* Refresh control. Bit 14 is enable. Bits<13:0> Refresh time */
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pbl_reg_writel 0x4186, DDR_REFRESH
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/* This register is used along with DQ Lane 0; DQ[7:0], DQS_0 */
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pbl_reg_writel 0x8, DDR_TAP_CTRL0
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/* This register is used along with DQ Lane 1; DQ[15:8], DQS_1 */
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pbl_reg_writel 0x9, DDR_TAP_CTRL1
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/*
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* DDR read and capture bit mask.
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* Each bit represents a cycle of valid data.
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* 0xff: use 16-bit DDR
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*/
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pbl_reg_writel 0xff, DDR_RD_DATA
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.set pop
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.endm
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.macro pbl_ar9331_ddr2_config
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.set push
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.set noreorder
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pbl_reg_writel 0x7fbc8cd0, DDR_CONFIG
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pbl_reg_writel 0x9dd0e6a8, DDR_CONFIG2
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/* Enable DDR2 */
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pbl_reg_writel 0x00000a59, DDR_DDR2_CONFIG
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pbl_reg_writel DDR_CTRL_PREA, DDR_CTRL
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/* Disable High Temperature Self-Refresh Rate */
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pbl_reg_writel 0x00000000, DDR_EMR2
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pbl_reg_writel DDR_CTRL_EMR2, DDR_CTRL
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pbl_reg_writel 0x00000000, DDR_EMR3
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pbl_reg_writel DDR_CTRL_EMR3, DDR_CTRL
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/* Enable DLL */
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pbl_reg_writel 0x00000000, DDR_EXT_MODE
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pbl_reg_writel DDR_CTRL_EMRS, DDR_CTRL
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/* Reset DLL */
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pbl_reg_writel 0x00000100, DDR_MODE
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pbl_reg_writel DDR_CTRL_MRS, DDR_CTRL
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pbl_reg_writel DDR_CTRL_PREA, DDR_CTRL
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pbl_reg_writel DDR_CTRL_REF, DDR_CTRL
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pbl_reg_writel DDR_CTRL_REF, DDR_CTRL
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/* Write recovery (WR) 6 clock, CAS Latency 3, Burst Length 8 */
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pbl_reg_writel 0x00000a33, DDR_MODE
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pbl_reg_writel DDR_CTRL_MRS, DDR_CTRL
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/*
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* DDR_EXT_MODE[9:7] = 0x7: (OCD Calibration defaults)
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* DDR_EXT_MODE[1] = 1: Reduced Drive Strength
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* DDR_EXT_MODE[0] = 0: Enable DLL
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*/
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pbl_reg_writel 0x00000382, DDR_EXT_MODE
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pbl_reg_writel DDR_CTRL_EMRS, DDR_CTRL
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/*
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* DDR_EXT_MODE[9:7] = 0x0: (OCD exit)
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* DDR_EXT_MODE[1] = 1: Reduced Drive Strength
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* DDR_EXT_MODE[0] = 0: Enable DLL
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*/
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pbl_reg_writel 0x00000402, DDR_EXT_MODE
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pbl_reg_writel DDR_CTRL_EMRS, DDR_CTRL
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/* Refresh control. Bit 14 is enable. Bits <13:0> Refresh time */
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pbl_reg_writel 0x00004186, DDR_REFRESH
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/* DQS 0 Tap Control (needs tuning) */
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pbl_reg_writel 0x00000008, DDR_TAP_CTRL0
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/* DQS 1 Tap Control (needs tuning) */
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pbl_reg_writel 0x00000009, DDR_TAP_CTRL1
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/* For 16-bit DDR */
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pbl_reg_writel 0x000000ff, DDR_RD_DATA
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.set pop
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.endm
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#define GPIO_FUNC ((KSEG1 | AR71XX_GPIO_BASE) | AR71XX_GPIO_REG_FUNC)
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.macro pbl_ar9331_uart_enable
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pbl_reg_set AR933X_GPIO_FUNC_UART_EN \
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| AR933X_GPIO_FUNC_RSRV15, GPIO_FUNC
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.endm
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#endif /* __ASM_MACH_ATH79_PBL_MACROS_H */
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