At least the iMX6 boot rom seems to jump into barebox with a non invalidated d-cache which causes data corruption when v7_mmu_cache_flush() executed by arm_early_mmu_cache_flush() overrides stack or other valid data. That's why the cache must be invalided for this processors explicitly (e.g. in barebox_arm_reset_vector()). Operation differs from flush only in one instruction so that patch modifies the existing v7_mmu_cache_flush() function slightly by adding an optional argument. Signed-off-by: Enrico Scholz <enrico.scholz@sigma-chemnitz.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
214 lines
6.1 KiB
ArmAsm
214 lines
6.1 KiB
ArmAsm
#include <linux/linkage.h>
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#include <init.h>
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.section .text.v7_mmu_cache_on
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ENTRY(v7_mmu_cache_on)
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stmfd sp!, {r11, lr}
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mov r12, lr
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#ifdef CONFIG_MMU
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mrc p15, 0, r11, c0, c1, 4 @ read ID_MMFR0
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tst r11, #0xf @ VMSA
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mov r0, #0
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mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
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tst r11, #0xf @ VMSA
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mcrne p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
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#endif
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mrc p15, 0, r0, c1, c0, 0 @ read control reg
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orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
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orr r0, r0, #0x003c @ write buffer
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#ifdef CONFIG_MMU
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#ifdef CONFIG_CPU_ENDIAN_BE8
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orr r0, r0, #1 << 25 @ big-endian page tables
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#endif
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orrne r0, r0, #1 @ MMU enabled
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movne r1, #-1
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mcrne p15, 0, r1, c3, c0, 0 @ load domain access control
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#endif
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mcr p15, 0, r0, c7, c5, 4 @ ISB
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mcr p15, 0, r0, c1, c0, 0 @ load control register
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mrc p15, 0, r0, c1, c0, 0 @ and read it back
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mov r0, #0
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mcr p15, 0, r0, c7, c5, 4 @ ISB
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ldmfd sp!, {r11, pc}
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ENDPROC(v7_mmu_cache_on)
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.section .text.v7_mmu_cache_off
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ENTRY(v7_mmu_cache_off)
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/* although 'r12' is an eabi scratch register which does
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not need to be restored, save it to ensure an 8-byte
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stack alignment */
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stmfd sp!, {r4-r12, lr}
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mrc p15, 0, r0, c1, c0
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#ifdef CONFIG_MMU
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bic r0, r0, #0x000d
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#else
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bic r0, r0, #0x000c
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#endif
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mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
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bl v7_mmu_cache_flush
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mov r0, #0
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#ifdef CONFIG_MMU
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mcr p15, 0, r0, c8, c7, 0 @ invalidate whole TLB
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#endif
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mcr p15, 0, r0, c7, c5, 6 @ invalidate BTC
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mcr p15, 0, r0, c7, c10, 4 @ DSB
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mcr p15, 0, r0, c7, c5, 4 @ ISB
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ldmfd sp!, {r4-r12, pc}
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ENDPROC(v7_mmu_cache_off)
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.section .text.v7_mmu_cache_flush_invalidate
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ENTRY(v7_mmu_cache_invalidate)
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mov r0, #1
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b __v7_mmu_cache_flush_invalidate
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ENDPROC(v7_mmu_cache_invalidate)
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ENTRY(v7_mmu_cache_flush)
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mov r0, #0
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b __v7_mmu_cache_flush_invalidate
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ENDPROC(v7_mmu_cache_flush)
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ENTRY(__v7_mmu_cache_flush_invalidate)
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mrc p15, 0, r12, c0, c1, 5 @ read ID_MMFR1
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tst r12, #0xf << 16 @ hierarchical cache (ARMv7)
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mov r12, #0
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beq hierarchical
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mcr p15, 0, r12, c7, c14, 0 @ clean+invalidate D
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b iflush
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hierarchical:
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stmfd sp!, {r4-r11}
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mov r8, r0
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mcr p15, 0, r12, c7, c10, 5 @ DMB
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mrc p15, 1, r0, c0, c0, 1 @ read clidr
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ands r3, r0, #0x7000000 @ extract loc from clidr
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mov r3, r3, lsr #23 @ left align loc bit field
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beq finished @ if loc is 0, then no need to clean
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mov r12, #0 @ start clean at cache level 0
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loop1:
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add r2, r12, r12, lsr #1 @ work out 3x current cache level
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mov r1, r0, lsr r2 @ extract cache type bits from clidr
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and r1, r1, #7 @ mask of the bits for current cache only
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cmp r1, #2 @ see what cache we have at this level
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blt skip @ skip if no cache, or just i-cache
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mcr p15, 2, r12, c0, c0, 0 @ select current cache level in cssr
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mcr p15, 0, r12, c7, c5, 4 @ isb to sych the new cssr&csidr
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mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
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and r2, r1, #7 @ extract the length of the cache lines
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add r2, r2, #4 @ add 4 (line length offset)
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ldr r4, =0x3ff
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ands r4, r4, r1, lsr #3 @ find maximum number on the way size
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clz r5, r4 @ find bit position of way size increment
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ldr r7, =0x7fff
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ands r7, r7, r1, lsr #13 @ extract max number of the index size
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loop2:
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mov r9, r4 @ create working copy of max way size
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loop3:
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ARM( orr r11, r12, r9, lsl r5 ) @ factor way and cache number into r11
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ARM( orr r11, r11, r7, lsl r2 ) @ factor index number into r11
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THUMB( lsl r6, r9, r5 )
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THUMB( orr r11, r12, r6 ) @ factor way and cache number into r11
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THUMB( lsl r6, r7, r2 )
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THUMB( orr r11, r11, r6 ) @ factor index number into r11
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cmp r8, #0
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THUMB( ite eq )
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mcreq p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way
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mcrne p15, 0, r11, c7, c6, 2 @ invalidate by set/way
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subs r9, r9, #1 @ decrement the way
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bge loop3
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subs r7, r7, #1 @ decrement the index
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bge loop2
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skip:
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add r12, r12, #2 @ increment cache number
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cmp r3, r12
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bgt loop1
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finished:
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ldmfd sp!, {r4-r11}
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mov r12, #0 @ switch back to cache level 0
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mcr p15, 2, r12, c0, c0, 0 @ select current cache level in cssr
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iflush:
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mcr p15, 0, r12, c7, c10, 4 @ DSB
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mcr p15, 0, r12, c7, c5, 0 @ invalidate I+BTB
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mcr p15, 0, r12, c7, c10, 4 @ DSB
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mcr p15, 0, r12, c7, c5, 4 @ ISB
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mov pc, lr
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ENDPROC(__v7_mmu_cache_flush_invalidate)
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/*
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* cache_line_size - get the cache line size from the CSIDR register
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* (available on ARMv7+). It assumes that the CSSR register was configured
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* to access the L1 data cache CSIDR.
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*/
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.macro dcache_line_size, reg, tmp
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mrc p15, 1, \tmp, c0, c0, 0 @ read CSIDR
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and \tmp, \tmp, #7 @ cache line size encoding
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mov \reg, #16 @ size offset
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mov \reg, \reg, lsl \tmp @ actual cache line size
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.endm
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/*
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* v7_dma_inv_range(start,end)
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*
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* Invalidate the data cache within the specified region; we will
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* be performing a DMA operation in this region and we want to
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* purge old data in the cache.
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*
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* - start - virtual start address of region
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* - end - virtual end address of region
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*/
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.section .text.v7_dma_inv_range
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ENTRY(v7_dma_inv_range)
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dcache_line_size r2, r3
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sub r3, r2, #1
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tst r0, r3
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bic r0, r0, r3
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mcrne p15, 0, r0, c7, c14, 1 @ clean & invalidate D / U line
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tst r1, r3
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bic r1, r1, r3
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mcrne p15, 0, r1, c7, c14, 1 @ clean & invalidate D / U line
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1:
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mcr p15, 0, r0, c7, c6, 1 @ invalidate D / U line
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add r0, r0, r2
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cmp r0, r1
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blo 1b
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dsb
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mov pc, lr
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ENDPROC(v7_dma_inv_range)
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/*
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* v7_dma_clean_range(start,end)
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* - start - virtual start address of region
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* - end - virtual end address of region
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*/
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.section .text.v7_dma_clean_range
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ENTRY(v7_dma_clean_range)
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dcache_line_size r2, r3
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sub r3, r2, #1
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bic r0, r0, r3
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1:
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mcr p15, 0, r0, c7, c10, 1 @ clean D / U line
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add r0, r0, r2
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cmp r0, r1
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blo 1b
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dsb
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mov pc, lr
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ENDPROC(v7_dma_clean_range)
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/*
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* v7_dma_flush_range(start,end)
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* - start - virtual start address of region
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* - end - virtual end address of region
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*/
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.section .text.v7_dma_flush_range
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ENTRY(v7_dma_flush_range)
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dcache_line_size r2, r3
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sub r3, r2, #1
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bic r0, r0, r3
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1:
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mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D / U line
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add r0, r0, r2
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cmp r0, r1
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blo 1b
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dsb
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mov pc, lr
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ENDPROC(v7_dma_flush_range)
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