d8753571b2
This file originates in Linux. Linux has it under include/linux/ directory since commit dccd2304cc90. Let's move it to the same place as well in barebox. This commit was generated by the following commands: find -name '*.[chS]' | xargs sed -i -e 's:<sizes.h>:<linux/sizes.h>:' git mv include/sizes.h include/linux/ Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
54 lines
1.1 KiB
C
54 lines
1.1 KiB
C
#include <common.h>
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#include <asm/mmu.h>
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#include <errno.h>
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#include <linux/sizes.h>
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#include <asm/memory.h>
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#include <asm/system.h>
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#include <asm/cache.h>
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#include "mmu.h"
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static uint32_t *ttb;
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static void create_sections(unsigned long addr, int size_m, unsigned int flags)
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{
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int i;
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addr >>= 20;
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for (i = size_m; i > 0; i--, addr++)
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ttb[addr] = (addr << 20) | flags;
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}
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static void map_cachable(unsigned long start, unsigned long size)
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{
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start &= ~(SZ_1M - 1);
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size = (size + (SZ_1M - 1)) & ~(SZ_1M - 1);
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create_sections(start, size >> 20, PMD_SECT_AP_WRITE |
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PMD_SECT_AP_READ | PMD_TYPE_SECT | PMD_SECT_WB);
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}
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void mmu_early_enable(uint32_t membase, uint32_t memsize, uint32_t _ttb)
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{
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int i;
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ttb = (uint32_t *)_ttb;
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arm_set_cache_functions();
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/* Set the ttb register */
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asm volatile ("mcr p15,0,%0,c2,c0,0" : : "r"(ttb) /*:*/);
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/* Set the Domain Access Control Register */
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i = 0x3;
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asm volatile ("mcr p15,0,%0,c3,c0,0" : : "r"(i) /*:*/);
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create_sections(0, 4096, PMD_SECT_AP_WRITE |
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PMD_SECT_AP_READ | PMD_TYPE_SECT);
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map_cachable(membase, memsize);
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__mmu_cache_on();
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}
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