452 lines
10 KiB
C
452 lines
10 KiB
C
/*
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* Copyright (c) 2009-2013 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2
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* as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#define pr_fmt(fmt) "mmu: " fmt
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#include <common.h>
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#include <dma-dir.h>
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#include <init.h>
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#include <asm/mmu.h>
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#include <errno.h>
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#include <linux/sizes.h>
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#include <asm/memory.h>
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#include <asm/barebox-arm.h>
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#include <asm/system.h>
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#include <asm/cache.h>
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#include <memory.h>
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#include <asm/system_info.h>
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#include "mmu.h"
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static unsigned long *ttb;
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static void create_sections(unsigned long virt, unsigned long phys, int size_m,
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unsigned int flags)
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{
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int i;
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phys >>= 20;
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virt >>= 20;
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for (i = size_m; i > 0; i--, virt++, phys++)
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ttb[virt] = (phys << 20) | flags;
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__mmu_cache_flush();
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}
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/*
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* Do it the simple way for now and invalidate the entire
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* tlb
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*/
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static inline void tlb_invalidate(void)
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{
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asm volatile (
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"mov r0, #0\n"
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"mcr p15, 0, r0, c7, c10, 4; @ drain write buffer\n"
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"mcr p15, 0, r0, c8, c6, 0; @ invalidate D TLBs\n"
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"mcr p15, 0, r0, c8, c5, 0; @ invalidate I TLBs\n"
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:
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:
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: "r0"
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);
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}
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#define PTE_FLAGS_CACHED_V7 (PTE_EXT_TEX(1) | PTE_BUFFERABLE | PTE_CACHEABLE)
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#define PTE_FLAGS_UNCACHED_V7 (0)
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#define PTE_FLAGS_CACHED_V4 (PTE_SMALL_AP_UNO_SRW | PTE_BUFFERABLE | PTE_CACHEABLE)
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#define PTE_FLAGS_UNCACHED_V4 PTE_SMALL_AP_UNO_SRW
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/*
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* PTE flags to set cached and uncached areas.
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* This will be determined at runtime.
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*/
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static uint32_t pte_flags_cached;
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static uint32_t pte_flags_uncached;
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#define PTE_MASK ((1 << 12) - 1)
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uint32_t mmu_get_pte_cached_flags()
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{
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return pte_flags_cached;
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}
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uint32_t mmu_get_pte_uncached_flags()
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{
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return pte_flags_uncached;
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}
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static void arm_mmu_not_initialized_error(void)
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{
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/*
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* This means:
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* - one of the MMU functions like dma_alloc_coherent
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* or remap_range is called too early, before the MMU is initialized
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* - Or the MMU initialization has failed earlier
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*/
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panic("MMU not initialized\n");
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}
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/*
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* Create a second level translation table for the given virtual address.
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* We initially create a flat uncached mapping on it.
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* Not yet exported, but may be later if someone finds use for it.
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*/
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static u32 *arm_create_pte(unsigned long virt)
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{
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u32 *table;
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int i;
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table = memalign(0x400, 0x400);
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if (!ttb)
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arm_mmu_not_initialized_error();
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ttb[virt >> 20] = (unsigned long)table | PMD_TYPE_TABLE;
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for (i = 0; i < 256; i++) {
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table[i] = virt | PTE_TYPE_SMALL | pte_flags_uncached;
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virt += PAGE_SIZE;
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}
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return table;
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}
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static u32 *find_pte(unsigned long adr)
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{
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u32 *table;
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if (!ttb)
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arm_mmu_not_initialized_error();
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if ((ttb[adr >> 20] & PMD_TYPE_MASK) != PMD_TYPE_TABLE) {
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struct memory_bank *bank;
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int i = 0;
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/*
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* This should only be called for page mapped memory inside our
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* memory banks. It's a bug to call it with section mapped memory
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* locations.
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*/
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pr_crit("%s: TTB for address 0x%08lx is not of type table\n",
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__func__, adr);
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pr_crit("Memory banks:\n");
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for_each_memory_bank(bank)
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pr_crit("#%d 0x%08lx - 0x%08lx\n", i, bank->start,
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bank->start + bank->size - 1);
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BUG();
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}
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/* find the coarse page table base address */
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table = (u32 *)(ttb[adr >> 20] & ~0x3ff);
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/* find second level descriptor */
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return &table[(adr >> PAGE_SHIFT) & 0xff];
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}
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static void dma_flush_range(unsigned long start, unsigned long end)
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{
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if (outer_cache.flush_range)
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outer_cache.flush_range(start, end);
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__dma_flush_range(start, end);
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}
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static void dma_inv_range(unsigned long start, unsigned long end)
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{
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if (outer_cache.inv_range)
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outer_cache.inv_range(start, end);
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__dma_inv_range(start, end);
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}
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void remap_range(void *_start, size_t size, uint32_t flags)
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{
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unsigned long start = (unsigned long)_start;
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u32 *p;
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int numentries, i;
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numentries = size >> PAGE_SHIFT;
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p = find_pte(start);
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for (i = 0; i < numentries; i++) {
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p[i] &= ~PTE_MASK;
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p[i] |= flags | PTE_TYPE_SMALL;
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}
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dma_flush_range((unsigned long)p,
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(unsigned long)p + numentries * sizeof(u32));
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tlb_invalidate();
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}
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void *map_io_sections(unsigned long phys, void *_start, size_t size)
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{
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unsigned long start = (unsigned long)_start, sec;
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phys >>= 20;
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for (sec = start; sec < start + size; sec += (1 << 20))
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ttb[sec >> 20] = (phys++ << 20) | PMD_SECT_DEF_UNCACHED;
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dma_flush_range((unsigned long)ttb, (unsigned long)ttb + 0x4000);
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tlb_invalidate();
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return _start;
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}
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/*
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* remap the memory bank described by mem cachable and
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* bufferable
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*/
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static int arm_mmu_remap_sdram(struct memory_bank *bank)
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{
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unsigned long phys = (unsigned long)bank->start;
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unsigned long ttb_start = phys >> 20;
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unsigned long ttb_end = (phys >> 20) + (bank->size >> 20);
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unsigned long num_ptes = bank->size >> 10;
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int i, pte;
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u32 *ptes;
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pr_debug("remapping SDRAM from 0x%08lx (size 0x%08lx)\n",
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phys, bank->size);
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/*
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* We replace each 1MiB section in this range with second level page
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* tables, therefore we must have 1Mib aligment here.
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*/
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if ((phys & (SZ_1M - 1)) || (bank->size & (SZ_1M - 1)))
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return -EINVAL;
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ptes = xmemalign(PAGE_SIZE, num_ptes * sizeof(u32));
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pr_debug("ptes: 0x%p ttb_start: 0x%08lx ttb_end: 0x%08lx\n",
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ptes, ttb_start, ttb_end);
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for (i = 0; i < num_ptes; i++) {
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ptes[i] = (phys + i * PAGE_SIZE) | PTE_TYPE_SMALL |
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pte_flags_cached;
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}
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pte = 0;
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for (i = ttb_start; i < ttb_end; i++) {
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ttb[i] = (unsigned long)(&ptes[pte]) | PMD_TYPE_TABLE |
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(0 << 4);
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pte += 256;
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}
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dma_flush_range((unsigned long)ttb, (unsigned long)ttb + 0x4000);
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dma_flush_range((unsigned long)ptes, num_ptes * sizeof(u32));
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tlb_invalidate();
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return 0;
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}
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/*
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* We have 8 exception vectors and the table consists of absolute
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* jumps, so we need 8 * 4 bytes for the instructions and another
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* 8 * 4 bytes for the addresses.
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*/
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#define ARM_VECTORS_SIZE (sizeof(u32) * 8 * 2)
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/*
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* Map vectors and zero page
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*/
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static void vectors_init(void)
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{
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u32 *exc, *zero = NULL;
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void *vectors;
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u32 cr;
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cr = get_cr();
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cr |= CR_V;
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set_cr(cr);
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cr = get_cr();
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if (cr & CR_V) {
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/*
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* If we can use high vectors, create the second level
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* page table for the high vectors and zero page
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*/
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exc = arm_create_pte(0xfff00000);
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zero = arm_create_pte(0x0);
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/* Set the zero page to faulting */
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zero[0] = 0;
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} else {
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/*
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* Otherwise map the vectors to the zero page. We have to
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* live without being able to catch NULL pointer dereferences
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*/
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exc = arm_create_pte(0x0);
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}
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arm_fixup_vectors();
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vectors = xmemalign(PAGE_SIZE, PAGE_SIZE);
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memset(vectors, 0, PAGE_SIZE);
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memcpy(vectors, __exceptions_start, __exceptions_stop - __exceptions_start);
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if (cr & CR_V)
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exc[256 - 16] = (u32)vectors | PTE_TYPE_SMALL |
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pte_flags_cached;
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else
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exc[0] = (u32)vectors | PTE_TYPE_SMALL | pte_flags_cached;
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}
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/*
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* Prepare MMU for usage enable it.
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*/
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static int mmu_init(void)
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{
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struct memory_bank *bank;
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int i;
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if (list_empty(&memory_banks))
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/*
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* If you see this it means you have no memory registered.
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* This can be done either with arm_add_mem_device() in an
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* initcall prior to mmu_initcall or via devicetree in the
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* memory node.
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*/
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panic("MMU: No memory bank found! Cannot continue\n");
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arm_set_cache_functions();
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if (cpu_architecture() >= CPU_ARCH_ARMv7) {
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pte_flags_cached = PTE_FLAGS_CACHED_V7;
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pte_flags_uncached = PTE_FLAGS_UNCACHED_V7;
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} else {
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pte_flags_cached = PTE_FLAGS_CACHED_V4;
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pte_flags_uncached = PTE_FLAGS_UNCACHED_V4;
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}
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if (get_cr() & CR_M) {
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/*
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* Early MMU code has already enabled the MMU. We assume a
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* flat 1:1 section mapping in this case.
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*/
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asm volatile ("mrc p15,0,%0,c2,c0,0" : "=r"(ttb));
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/* Clear unpredictable bits [13:0] */
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ttb = (unsigned long *)((unsigned long)ttb & ~0x3fff);
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if (!request_sdram_region("ttb", (unsigned long)ttb, SZ_16K))
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/*
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* This can mean that:
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* - the early MMU code has put the ttb into a place
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* which we don't have inside our available memory
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* - Somebody else has occupied the ttb region which means
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* the ttb will get corrupted.
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*/
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pr_crit("Critical Error: Can't request SDRAM region for ttb at %p\n",
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ttb);
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} else {
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ttb = memalign(0x10000, 0x4000);
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}
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pr_debug("ttb: 0x%p\n", ttb);
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/* Set the ttb register */
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asm volatile ("mcr p15,0,%0,c2,c0,0" : : "r"(ttb) /*:*/);
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/* Set the Domain Access Control Register */
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i = 0x3;
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asm volatile ("mcr p15,0,%0,c3,c0,0" : : "r"(i) /*:*/);
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/* create a flat mapping using 1MiB sections */
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create_sections(0, 0, PAGE_SIZE, PMD_SECT_AP_WRITE | PMD_SECT_AP_READ |
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PMD_TYPE_SECT);
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vectors_init();
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/*
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* First remap sdram cached using sections.
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* This is to speed up the generation of 2nd level page tables
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* below
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*/
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for_each_memory_bank(bank)
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create_sections(bank->start, bank->start, bank->size >> 20,
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PMD_SECT_DEF_CACHED);
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__mmu_cache_on();
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/*
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* Now that we have the MMU and caches on remap sdram again using
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* page tables
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*/
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for_each_memory_bank(bank)
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arm_mmu_remap_sdram(bank);
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return 0;
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}
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mmu_initcall(mmu_init);
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void *dma_alloc_coherent(size_t size, dma_addr_t *dma_handle)
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{
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void *ret;
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size = PAGE_ALIGN(size);
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ret = xmemalign(PAGE_SIZE, size);
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if (dma_handle)
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*dma_handle = (dma_addr_t)ret;
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dma_inv_range((unsigned long)ret, (unsigned long)ret + size);
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remap_range(ret, size, pte_flags_uncached);
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return ret;
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}
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unsigned long virt_to_phys(volatile void *virt)
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{
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return (unsigned long)virt;
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}
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void *phys_to_virt(unsigned long phys)
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{
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return (void *)phys;
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}
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void dma_free_coherent(void *mem, dma_addr_t dma_handle, size_t size)
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{
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size = PAGE_ALIGN(size);
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remap_range(mem, size, pte_flags_cached);
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free(mem);
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}
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void dma_sync_single_for_cpu(unsigned long address, size_t size,
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enum dma_data_direction dir)
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{
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if (dir != DMA_TO_DEVICE) {
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if (outer_cache.inv_range)
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outer_cache.inv_range(address, address + size);
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__dma_inv_range(address, address + size);
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}
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}
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void dma_sync_single_for_device(unsigned long address, size_t size,
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enum dma_data_direction dir)
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{
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if (dir == DMA_FROM_DEVICE) {
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__dma_inv_range(address, address + size);
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if (outer_cache.inv_range)
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outer_cache.inv_range(address, address + size);
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} else {
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__dma_clean_range(address, address + size);
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if (outer_cache.clean_range)
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outer_cache.clean_range(address, address + size);
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}
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}
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