Mostly to make it clear that boarddata needs to be something we can dereference. As this is a pretty invasive change, use the opportunity to make the signature 64bit safe. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
134 lines
2.8 KiB
C
134 lines
2.8 KiB
C
/*
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* Copyright (C) 2009-2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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*
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* Under GPLv2
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*/
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#define __LOWLEVEL_INIT__
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#include <common.h>
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#include <asm/system.h>
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#include <asm/barebox-arm.h>
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#include <asm/barebox-arm-head.h>
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#include <mach/hardware.h>
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#include <mach/at91rm9200.h>
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#include <mach/at91rm9200_mc.h>
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#include <mach/at91_pio.h>
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#include <mach/at91_pmc.h>
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#include <mach/io.h>
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#include <init.h>
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void static inline access_sdram(void)
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{
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writel(0x00000000, AT91_SDRAM_BASE);
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}
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void __naked __bare_init barebox_arm_reset_vector(void)
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{
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u32 r;
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int i;
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arm_cpu_lowlevel_init();
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/*
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* PMC Check if the PLL is already initialized
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*/
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r = at91_pmc_read(AT91_PMC_MCKR);
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if (r & AT91_PMC_CSS)
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goto end;
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/*
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* Enable the Main Oscillator
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*/
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at91_pmc_write(AT91_CKGR_MOR, CONFIG_SYS_MOR_VAL);
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do {
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r = at91_pmc_read(AT91_PMC_SR);
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} while (!(r & AT91_PMC_MOSCS));
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/*
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* EBI_CFGR
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*/
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at91_sys_write(AT91_EBI_CFGR, CONFIG_SYS_EBI_CFGR_VAL);
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/*
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* SMC2_CSR[0]: 16bit, 2 TDF, 4 WS
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*/
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at91_sys_write(AT91_SMC_CSR(0), CONFIG_SYS_SMC_CSR0_VAL);
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/*
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* Init Clocks
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*/
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/*
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* PLLAR: x MHz for PCK
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*/
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at91_pmc_write(AT91_CKGR_PLLAR, CONFIG_SYS_PLLAR_VAL);
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do {
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r = at91_pmc_read(AT91_PMC_SR);
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} while (!(r & AT91_PMC_LOCKA));
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/*
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* PCK/x = MCK Master Clock from SLOW
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*/
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at91_pmc_write(AT91_PMC_MCKR, CONFIG_SYS_MCKR2_VAL1);
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/*
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* PCK/x = MCK Master Clock from PLLA
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*/
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at91_pmc_write(AT91_PMC_MCKR, CONFIG_SYS_MCKR2_VAL2);
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do {
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r = at91_pmc_read(AT91_PMC_SR);
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} while (!(r & AT91_PMC_MCKRDY));
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/*
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* Init SDRAM
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*/
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/* PIOC_ASR: Configure PIOC as peripheral (D16/D31) */
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__raw_writel(CONFIG_SYS_PIOC_ASR_VAL, AT91_BASE_PIOC + PIO_ASR);
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/* PIOC_BSR */
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__raw_writel(CONFIG_SYS_PIOC_BSR_VAL, AT91_BASE_PIOC + PIO_BSR);
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/* PIOC_PDR */
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__raw_writel(CONFIG_SYS_PIOC_PDR_VAL, AT91_BASE_PIOC + PIO_PDR);
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/* EBI_CSA : CS1=SDRAM */
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at91_sys_write(AT91_EBI_CSA, CONFIG_SYS_EBI_CSA_VAL);
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/* SDRC_CR */
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at91_sys_write(AT91_SDRAMC_CR, CONFIG_SYS_SDRC_CR_VAL);
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/* SDRC_MR : Precharge All */
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at91_sys_write(AT91_SDRAMC_MR, AT91_SDRAMC_MODE_PRECHARGE);
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/* access SDRAM */
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access_sdram();
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/* SDRC_MR : refresh */
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at91_sys_write(AT91_SDRAMC_MR, AT91_SDRAMC_MODE_REFRESH);
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/* access SDRAM 8 times */
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for (i = 0; i < 8; i++)
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access_sdram();
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/* SDRC_MR : Load Mode Register */
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at91_sys_write(AT91_SDRAMC_MR, AT91_SDRAMC_MODE_LMR);
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/* access SDRAM */
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access_sdram();
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/* SDRC_TR : Write refresh rate */
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at91_sys_write(AT91_SDRAMC_TR, CONFIG_SYS_SDRC_TR_VAL);
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/* access SDRAM */
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access_sdram();
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/* SDRC_MR : Normal Mode */
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at91_sys_write(AT91_SDRAMC_MR, AT91_SDRAMC_MODE_NORMAL);
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/* access SDRAM */
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access_sdram();
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/* switch from FastBus to Asynchronous clock mode */
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r = get_cr();
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r |= 0xC0000000; /* set bit 31 (iA) and 30 (nF) */
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set_cr(r);
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end:
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barebox_arm_entry(AT91_CHIPSELECT_1, at91rm9200_get_sdram_size(), NULL);
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}
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