Some drivers need clk_set_rate. To be able to link with these drivers enabled provide a clk_set_rate stub. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
922 lines
22 KiB
C
922 lines
22 KiB
C
/*
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* linux/arch/arm/mach-at91/clock.c
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*
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* Copyright (C) 2005 David Brownell
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* Copyright (C) 2005 Ivan Kokshaysky
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <common.h>
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#include <command.h>
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#include <complete.h>
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#include <linux/list.h>
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#include <errno.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <init.h>
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#include <mach/hardware.h>
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#include <mach/io.h>
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#include <mach/at91_pmc.h>
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#include <mach/cpu.h>
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#include "clock.h"
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#include "generic.h"
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/*
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* There's a lot more which can be done with clocks, including cpufreq
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* integration, slow clock mode support (for system suspend), letting
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* PLLB be used at other rates (on boards that don't need USB), etc.
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*/
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#define clk_is_primary(x) ((x)->type & CLK_TYPE_PRIMARY)
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#define clk_is_programmable(x) ((x)->type & CLK_TYPE_PROGRAMMABLE)
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#define clk_is_peripheral(x) ((x)->type & CLK_TYPE_PERIPHERAL)
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#define clk_is_sys(x) ((x)->type & CLK_TYPE_SYSTEM)
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#define clk_is_periph_h64mx(x) ((x)->type & CLK_TYPE_PERIPH_H64MX)
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/*
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* Chips have some kind of clocks : group them by functionality
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*/
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#define cpu_has_utmi() ( cpu_is_at91sam9rl() \
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|| cpu_is_at91sam9g45() \
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|| cpu_is_at91sam9x5() \
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|| cpu_is_sama5d3() \
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|| cpu_is_sama5d4())
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#define cpu_has_1200M_plla() (cpu_is_sama5d4())
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#define cpu_has_1056M_plla() (cpu_is_sama5d3())
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#define cpu_has_800M_plla() ( cpu_is_at91sam9g20() \
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|| cpu_is_at91sam9g45() \
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|| cpu_is_at91sam9x5() \
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|| cpu_is_at91sam9n12())
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#define cpu_has_300M_plla() (cpu_is_at91sam9g10())
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#define cpu_has_240M_plla() (cpu_is_at91sam9261() \
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|| cpu_is_at91sam9263() \
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|| cpu_is_at91sam9rl())
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#define cpu_has_210M_plla() (cpu_is_at91sam9260())
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#define cpu_has_pllb() (!(cpu_is_at91sam9rl() \
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|| cpu_is_at91sam9g45() \
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|| cpu_is_at91sam9x5() \
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|| cpu_is_sama5d3() \
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|| cpu_is_sama5d4()))
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#define cpu_has_upll() (cpu_is_at91sam9g45() \
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|| cpu_is_at91sam9x5() \
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|| cpu_is_sama5d3() \
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|| cpu_is_sama5d4())
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/* USB host HS & FS */
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#define cpu_has_uhp() (!cpu_is_at91sam9rl())
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/* USB device FS only */
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#define cpu_has_udpfs() (!(cpu_is_at91sam9rl() \
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|| cpu_is_at91sam9g45() \
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|| cpu_is_at91sam9x5() \
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|| cpu_is_sama5d3() \
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|| cpu_is_sama5d4()))
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#define cpu_has_plladiv2() (cpu_is_at91sam9g45() \
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|| cpu_is_at91sam9x5() \
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|| cpu_is_at91sam9n12() \
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|| cpu_is_sama5d3() \
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|| cpu_is_sama5d4())
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#define cpu_has_mdiv3() (cpu_is_at91sam9g45() \
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|| cpu_is_at91sam9x5() \
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|| cpu_is_at91sam9n12() \
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|| cpu_is_sama5d3() \
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|| cpu_is_sama5d4())
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#define cpu_has_alt_prescaler() (cpu_is_at91sam9x5() \
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|| cpu_is_at91sam9n12() \
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|| cpu_is_sama5d3() \
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|| cpu_is_sama5d4())
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#define cpu_has_pcr() (cpu_is_sama5d3() \
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|| cpu_is_sama5d4())
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#define cpu_has_dual_matrix() (cpu_is_sama5d4())
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static LIST_HEAD(clocks);
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static u32 at91_pllb_usb_init;
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/*
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* Four primary clock sources: two crystal oscillators (32K, main), and
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* two PLLs. PLLA usually runs the master clock; and PLLB must run at
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* 48 MHz (unless no USB function clocks are needed). The main clock and
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* both PLLs are turned off to run in "slow clock mode" (system suspend).
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*/
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static struct clk clk32k = {
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.name = "clk32k",
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.rate_hz = AT91_SLOW_CLOCK,
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.users = 1, /* always on */
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.id = 0,
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.type = CLK_TYPE_PRIMARY,
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};
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static struct clk main_clk = {
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.name = "main",
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.pmc_mask = AT91_PMC_MOSCS, /* in PMC_SR */
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.id = 1,
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.type = CLK_TYPE_PRIMARY,
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};
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static struct clk plla = {
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.name = "plla",
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.parent = &main_clk,
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.pmc_mask = AT91_PMC_LOCKA, /* in PMC_SR */
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.id = 2,
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.type = CLK_TYPE_PRIMARY | CLK_TYPE_PLL,
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};
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static void pllb_mode(struct clk *clk, int is_on)
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{
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u32 value;
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if (is_on) {
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is_on = AT91_PMC_LOCKB;
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value = at91_pllb_usb_init;
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} else
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value = 0;
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// REVISIT: Add work-around for AT91RM9200 Errata #26 ?
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at91_pmc_write(AT91_CKGR_PLLBR, value);
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do {
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barrier();
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} while ((at91_pmc_read(AT91_PMC_SR) & AT91_PMC_LOCKB) != is_on);
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}
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static struct clk pllb = {
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.name = "pllb",
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.parent = &main_clk,
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.pmc_mask = AT91_PMC_LOCKB, /* in PMC_SR */
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.mode = pllb_mode,
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.id = 3,
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.type = CLK_TYPE_PRIMARY | CLK_TYPE_PLL,
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};
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static void pmc_sys_mode(struct clk *clk, int is_on)
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{
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if (is_on)
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at91_pmc_write(AT91_PMC_SCER, clk->pmc_mask);
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else
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at91_pmc_write(AT91_PMC_SCDR, clk->pmc_mask);
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}
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static void pmc_uckr_mode(struct clk *clk, int is_on)
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{
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unsigned int uckr = at91_pmc_read(AT91_CKGR_UCKR);
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if (cpu_is_at91sam9g45()) {
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if (is_on)
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uckr |= AT91_PMC_BIASEN;
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else
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uckr &= ~AT91_PMC_BIASEN;
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}
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if (is_on) {
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is_on = AT91_PMC_LOCKU;
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at91_pmc_write(AT91_CKGR_UCKR, uckr | clk->pmc_mask);
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} else
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at91_pmc_write(AT91_CKGR_UCKR, uckr & ~(clk->pmc_mask));
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do {
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barrier();
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} while ((at91_pmc_read(AT91_PMC_SR) & AT91_PMC_LOCKU) != is_on);
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}
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/* USB function clocks (PLLB must be 48 MHz) */
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static struct clk udpck = {
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.name = "udpck",
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.parent = &pllb,
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.mode = pmc_sys_mode,
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};
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struct clk utmi_clk = {
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.name = "utmi_clk",
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.parent = &main_clk,
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.pmc_mask = AT91_PMC_UPLLEN, /* in CKGR_UCKR */
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.mode = pmc_uckr_mode,
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.type = CLK_TYPE_PLL,
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};
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static struct clk uhpck = {
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.name = "uhpck",
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/*.parent = ... we choose parent at runtime */
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.mode = pmc_sys_mode,
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};
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/*
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* The master clock is divided from the CPU clock (by 1-4). It's used for
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* memory, interfaces to on-chip peripherals, the AIC, and sometimes more
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* (e.g baud rate generation). It's sourced from one of the primary clocks.
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*/
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struct clk mck = {
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.name = "mck",
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.pmc_mask = AT91_PMC_MCKRDY, /* in PMC_SR */
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};
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struct clk h32mx_clk = {
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.name = "h32mx",
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.parent = &mck,
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.pmc_mask = AT91_PMC_H32MXDIV, /* in PMC_MCKR */
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};
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static void pmc_periph_mode(struct clk *clk, int is_on)
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{
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u32 regval = 0;
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/*
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* With sama5d3 chips, you have more than 32 peripherals so only one
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* register is not enough to manage their clocks. A peripheral
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* control register has been introduced to solve this issue.
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*/
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if (cpu_has_pcr()) {
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regval |= AT91_PMC_PCR_CMD; /* write command */
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regval |= clk->pid & AT91_PMC_PCR_PID; /* peripheral selection */
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regval |= AT91_PMC_PCR_DIV(clk->div);
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if (is_on)
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regval |= AT91_PMC_PCR_EN; /* enable clock */
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at91_pmc_write(AT91_PMC_PCR, regval);
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} else {
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if (is_on)
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at91_pmc_write(AT91_PMC_PCER, clk->pmc_mask);
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else
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at91_pmc_write(AT91_PMC_PCDR, clk->pmc_mask);
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}
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}
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static struct clk *at91_css_to_clk(unsigned long css)
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{
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switch (css) {
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case AT91_PMC_CSS_SLOW:
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return &clk32k;
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case AT91_PMC_CSS_MAIN:
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return &main_clk;
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case AT91_PMC_CSS_PLLA:
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return &plla;
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case AT91_PMC_CSS_PLLB:
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if (cpu_has_upll())
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/* CSS_PLLB == CSS_UPLL */
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return &utmi_clk;
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else if (cpu_has_pllb())
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return &pllb;
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break;
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/* alternate PMC: can use master clock */
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case AT91_PMC_CSS_MASTER:
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return &mck;
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}
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return NULL;
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}
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static int pmc_prescaler_divider(u32 reg)
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{
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if (cpu_has_alt_prescaler()) {
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return 1 << ((reg & AT91_PMC_ALT_PRES) >> PMC_ALT_PRES_OFFSET);
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} else {
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return 1 << ((reg & AT91_PMC_PRES) >> PMC_PRES_OFFSET);
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}
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}
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static void __clk_enable(struct clk *clk)
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{
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if (clk->parent)
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__clk_enable(clk->parent);
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if (clk->users++ == 0 && clk->mode)
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clk->mode(clk, 1);
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}
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int clk_enable(struct clk *clk)
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{
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__clk_enable(clk);
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return 0;
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}
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EXPORT_SYMBOL(clk_enable);
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static void __clk_disable(struct clk *clk)
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{
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BUG_ON(clk->users == 0);
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if (--clk->users == 0 && clk->mode)
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clk->mode(clk, 0);
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if (clk->parent)
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__clk_disable(clk->parent);
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}
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void clk_disable(struct clk *clk)
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{
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__clk_disable(clk);
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}
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EXPORT_SYMBOL(clk_disable);
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unsigned long clk_get_rate(struct clk *clk)
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{
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unsigned long rate;
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for (;;) {
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rate = clk->rate_hz;
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if (rate || !clk->parent)
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break;
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clk = clk->parent;
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}
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return rate;
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}
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EXPORT_SYMBOL(clk_get_rate);
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/*------------------------------------------------------------------------*/
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/*
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* For now, only the programmable clocks support reparenting (MCK could
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* do this too, with care) or rate changing (the PLLs could do this too,
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* ditto MCK but that's more for cpufreq). Drivers may reparent to get
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* a better rate match; we don't.
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*/
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long clk_round_rate(struct clk *clk, unsigned long rate)
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{
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unsigned prescale;
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unsigned long actual;
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unsigned long prev = ULONG_MAX;
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if (!clk_is_programmable(clk))
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return -EINVAL;
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actual = clk->parent->rate_hz;
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for (prescale = 0; prescale < 7; prescale++) {
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if (actual > rate)
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prev = actual;
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if (actual && actual <= rate) {
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if ((prev - rate) < (rate - actual)) {
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actual = prev;
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prescale--;
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}
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break;
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}
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actual >>= 1;
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}
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return (prescale < 7) ? actual : -ENOENT;
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}
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EXPORT_SYMBOL(clk_round_rate);
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int clk_set_rate(struct clk *clk, unsigned long rate)
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{
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unsigned prescale;
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unsigned long prescale_offset, css_mask;
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unsigned long actual;
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if (!IS_ENABLED(CONFIG_PROGRAMMABLE_CLOCKS))
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return 0;
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if (!clk_is_programmable(clk))
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return -EINVAL;
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if (clk->users)
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return -EBUSY;
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if (cpu_has_alt_prescaler()) {
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prescale_offset = PMC_ALT_PRES_OFFSET;
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css_mask = AT91_PMC_ALT_PCKR_CSS;
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} else {
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prescale_offset = PMC_PRES_OFFSET;
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css_mask = AT91_PMC_CSS;
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}
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actual = clk->parent->rate_hz;
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for (prescale = 0; prescale < 7; prescale++) {
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if (actual && actual <= rate) {
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u32 pckr;
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pckr = at91_pmc_read(AT91_PMC_PCKR(clk->id));
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pckr &= css_mask; /* keep clock selection */
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pckr |= prescale << prescale_offset;
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at91_pmc_write(AT91_PMC_PCKR(clk->id), pckr);
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clk->rate_hz = actual;
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break;
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}
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actual >>= 1;
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}
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return (prescale < 7) ? actual : -ENOENT;
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}
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EXPORT_SYMBOL(clk_set_rate);
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struct clk *clk_get_parent(struct clk *clk)
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{
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return clk->parent;
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}
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EXPORT_SYMBOL(clk_get_parent);
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int clk_set_parent(struct clk *clk, struct clk *parent)
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{
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if (!IS_ENABLED(CONFIG_PROGRAMMABLE_CLOCKS))
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return -ENOSYS;
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if (clk->users)
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return -EBUSY;
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if (!clk_is_primary(parent) || !clk_is_programmable(clk))
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return -EINVAL;
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if (cpu_is_at91sam9rl() && parent->id == AT91_PMC_CSS_PLLB)
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return -EINVAL;
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clk->rate_hz = parent->rate_hz;
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clk->parent = parent;
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at91_pmc_write(AT91_PMC_PCKR(clk->id), parent->id);
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return 0;
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}
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EXPORT_SYMBOL(clk_set_parent);
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/* establish PCK0..PCKN parentage and rate */
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static void init_programmable_clock(struct clk *clk)
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{
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struct clk *parent;
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u32 pckr;
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unsigned int css_mask;
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if (cpu_has_alt_prescaler())
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css_mask = AT91_PMC_ALT_PCKR_CSS;
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else
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css_mask = AT91_PMC_CSS;
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pckr = at91_pmc_read(AT91_PMC_PCKR(clk->id));
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parent = at91_css_to_clk(pckr & css_mask);
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clk->parent = parent;
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clk->rate_hz = parent->rate_hz / pmc_prescaler_divider(pckr);
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}
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/*------------------------------------------------------------------------*/
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/* Register a new clock */
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static void __init at91_clk_add(struct clk *clk)
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{
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list_add_tail(&clk->node, &clocks);
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clk->cl.con_id = clk->name;
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clk->cl.clk = clk;
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clkdev_add(&clk->cl);
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}
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int clk_register(struct clk *clk)
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{
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if (clk_is_peripheral(clk)) {
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if (!clk->parent) {
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if (!cpu_has_dual_matrix() || clk_is_periph_h64mx(clk))
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clk->parent = &mck;
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else
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clk->parent = &h32mx_clk;
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}
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if (cpu_has_pcr())
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clk->rate_hz = DIV_ROUND_UP(clk->parent->rate_hz, 1 << clk->div);
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clk->mode = pmc_periph_mode;
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}
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else if (clk_is_sys(clk)) {
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clk->parent = &mck;
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clk->mode = pmc_sys_mode;
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} else if (IS_ENABLED(CONFIG_PROGRAMMABLE_CLOCKS) && clk_is_programmable(clk)) {
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clk->mode = pmc_sys_mode;
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init_programmable_clock(clk);
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}
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at91_clk_add(clk);
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return 0;
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}
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/*------------------------------------------------------------------------*/
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static u32 at91_pll_rate(struct clk *pll, u32 freq, u32 reg)
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{
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unsigned mul, div;
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div = reg & 0xff;
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if (cpu_is_sama5d3() || cpu_is_sama5d4())
|
|
mul = (reg >> 18) & 0x7ff;
|
|
else
|
|
mul = (reg >> 16) & 0x7ff;
|
|
if (div && mul) {
|
|
freq /= div;
|
|
freq *= mul + 1;
|
|
} else
|
|
freq = 0;
|
|
|
|
return freq;
|
|
}
|
|
|
|
static u32 at91_usb_rate(struct clk *pll, u32 freq, u32 reg)
|
|
{
|
|
if (pll == &pllb && (reg & AT91_PMC_USB96M))
|
|
return freq / 2;
|
|
else
|
|
return freq;
|
|
}
|
|
|
|
static unsigned at91_pll_calc(unsigned main_freq, unsigned out_freq)
|
|
{
|
|
unsigned i, div = 0, mul = 0, diff = 1 << 30;
|
|
unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00;
|
|
|
|
/* PLL output max 240 MHz (or 180 MHz per errata) */
|
|
if (out_freq > 240000000)
|
|
goto fail;
|
|
|
|
for (i = 1; i < 256; i++) {
|
|
int diff1;
|
|
unsigned input, mul1;
|
|
|
|
/*
|
|
* PLL input between 1MHz and 32MHz per spec, but lower
|
|
* frequences seem necessary in some cases so allow 100K.
|
|
* Warning: some newer products need 2MHz min.
|
|
*/
|
|
input = main_freq / i;
|
|
if (cpu_is_at91sam9g20() && input < 2000000)
|
|
continue;
|
|
if (input < 100000)
|
|
continue;
|
|
if (input > 32000000)
|
|
continue;
|
|
|
|
mul1 = out_freq / input;
|
|
if (cpu_is_at91sam9g20() && mul > 63)
|
|
continue;
|
|
if (mul1 > 2048)
|
|
continue;
|
|
if (mul1 < 2)
|
|
goto fail;
|
|
|
|
diff1 = out_freq - input * mul1;
|
|
if (diff1 < 0)
|
|
diff1 = -diff1;
|
|
if (diff > diff1) {
|
|
diff = diff1;
|
|
div = i;
|
|
mul = mul1;
|
|
if (diff == 0)
|
|
break;
|
|
}
|
|
}
|
|
if (i == 256 && diff > (out_freq >> 5))
|
|
goto fail;
|
|
return ret | ((mul - 1) << 16) | div;
|
|
fail:
|
|
return 0;
|
|
}
|
|
|
|
static struct clk *const standard_pmc_clocks[] = {
|
|
/* four primary clocks */
|
|
&clk32k,
|
|
&main_clk,
|
|
&plla,
|
|
|
|
/* MCK */
|
|
&mck
|
|
};
|
|
|
|
/* PLLB generated USB full speed clock init */
|
|
static void at91_pllb_usbfs_clock_init(unsigned long main_clock)
|
|
{
|
|
/*
|
|
* USB clock init: choose 48 MHz PLLB value,
|
|
* disable 48MHz clock during usb peripheral suspend.
|
|
*
|
|
* REVISIT: assumes MCK doesn't derive from PLLB!
|
|
*/
|
|
uhpck.parent = &pllb;
|
|
|
|
at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | AT91_PMC_USB96M;
|
|
pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init);
|
|
if (cpu_is_at91rm9200()) {
|
|
uhpck.pmc_mask = AT91RM9200_PMC_UHP;
|
|
udpck.pmc_mask = AT91RM9200_PMC_UDP;
|
|
at91_pmc_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP);
|
|
} else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() ||
|
|
cpu_is_at91sam9263() || cpu_is_at91sam9g20() ||
|
|
cpu_is_at91sam9g10()) {
|
|
uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
|
|
udpck.pmc_mask = AT91SAM926x_PMC_UDP;
|
|
}
|
|
at91_pmc_write(AT91_CKGR_PLLBR, 0);
|
|
|
|
udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
|
|
uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
|
|
}
|
|
|
|
/* UPLL generated USB full speed clock init */
|
|
static void at91_upll_usbfs_clock_init(unsigned long main_clock)
|
|
{
|
|
/*
|
|
* USB clock init: choose 480 MHz from UPLL,
|
|
*/
|
|
unsigned int usbr = AT91_PMC_USBS_UPLL;
|
|
|
|
/* Setup divider by 10 to reach 48 MHz */
|
|
usbr |= ((10 - 1) << 8) & AT91_PMC_OHCIUSBDIV;
|
|
|
|
at91_pmc_write(AT91_PMC_USB, usbr);
|
|
|
|
/* Now set uhpck values */
|
|
uhpck.parent = &utmi_clk;
|
|
uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
|
|
uhpck.rate_hz = utmi_clk.rate_hz;
|
|
uhpck.rate_hz /= 1 + ((at91_pmc_read(AT91_PMC_USB) & AT91_PMC_OHCIUSBDIV) >> 8);
|
|
}
|
|
|
|
static int pll_overclock = 0;
|
|
static u32 cpu_freq = 0;
|
|
static unsigned long at91_main_clock = 0;
|
|
|
|
void at91_set_main_clock(unsigned long rate)
|
|
{
|
|
at91_main_clock = rate;
|
|
}
|
|
|
|
int at91_clock_init(void)
|
|
{
|
|
unsigned tmp, freq, mckr;
|
|
int i;
|
|
unsigned long main_clock;
|
|
|
|
main_clock = at91_main_clock;
|
|
|
|
/*
|
|
* When the bootloader initialized the main oscillator correctly,
|
|
* there's no problem using the cycle counter. But if it didn't,
|
|
* or when using oscillator bypass mode, we must be told the speed
|
|
* of the main clock.
|
|
*/
|
|
if (!main_clock) {
|
|
do {
|
|
tmp = at91_pmc_read(AT91_CKGR_MCFR);
|
|
} while (!(tmp & AT91_PMC_MAINRDY));
|
|
main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16);
|
|
}
|
|
main_clk.rate_hz = main_clock;
|
|
|
|
/* report if PLLA is more than mildly overclocked */
|
|
plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_pmc_read(AT91_CKGR_PLLAR));
|
|
if (cpu_has_1200M_plla()) {
|
|
if (plla.rate_hz > 1200000000)
|
|
pll_overclock = 1;
|
|
} else if (cpu_has_1056M_plla()) {
|
|
if (plla.rate_hz > 1056000000)
|
|
pll_overclock = 1;
|
|
} else if (cpu_has_300M_plla()) {
|
|
if (plla.rate_hz > 300000000)
|
|
pll_overclock = 1;
|
|
} else if (cpu_has_800M_plla()) {
|
|
if (plla.rate_hz > 800000000)
|
|
pll_overclock = 1;
|
|
} else if (cpu_has_300M_plla()) {
|
|
if (plla.rate_hz > 300000000)
|
|
pll_overclock = 1;
|
|
} else if (cpu_has_240M_plla()) {
|
|
if (plla.rate_hz > 240000000)
|
|
pll_overclock = 1;
|
|
} else if (cpu_has_210M_plla()) {
|
|
if (plla.rate_hz > 210000000)
|
|
pll_overclock = 1;
|
|
} else {
|
|
if (plla.rate_hz > 209000000)
|
|
pll_overclock = 1;
|
|
}
|
|
|
|
if (cpu_has_plladiv2()) {
|
|
mckr = at91_pmc_read(AT91_PMC_MCKR);
|
|
plla.rate_hz /= (1 << ((mckr & AT91_PMC_PLLADIV2) >> 12)); /* plla divisor by 2 */
|
|
}
|
|
|
|
if (!cpu_has_pllb() && cpu_has_upll()) {
|
|
/* setup UTMI clock as the fourth primary clock
|
|
* (instead of pllb) */
|
|
utmi_clk.type |= CLK_TYPE_PRIMARY;
|
|
utmi_clk.id = 3;
|
|
}
|
|
|
|
/*
|
|
* USB HS clock init
|
|
*/
|
|
if (cpu_has_utmi()) {
|
|
/*
|
|
* multiplier is hard-wired to 40
|
|
* (obtain the USB High Speed 480 MHz when input is 12 MHz)
|
|
*/
|
|
utmi_clk.rate_hz = 40 * utmi_clk.parent->rate_hz;
|
|
|
|
/* UTMI bias and PLL are managed at the same time */
|
|
if (cpu_has_upll())
|
|
utmi_clk.pmc_mask |= AT91_PMC_BIASEN;
|
|
}
|
|
|
|
/*
|
|
* USB FS clock init
|
|
*/
|
|
if (cpu_has_pllb())
|
|
at91_pllb_usbfs_clock_init(main_clock);
|
|
if (cpu_has_upll())
|
|
/* assumes that we choose UPLL for USB and not PLLA */
|
|
at91_upll_usbfs_clock_init(main_clock);
|
|
|
|
/*
|
|
* MCK and CPU derive from one of those primary clocks.
|
|
* For now, assume this parentage won't change.
|
|
*/
|
|
mckr = at91_pmc_read(AT91_PMC_MCKR);
|
|
mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS);
|
|
freq = mck.parent->rate_hz;
|
|
freq /= pmc_prescaler_divider(mckr); /* prescale */
|
|
if (cpu_is_at91rm9200()) {
|
|
mck.rate_hz = freq / (1 + ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
|
|
} else if (cpu_is_at91sam9g20()) {
|
|
mck.rate_hz = (mckr & AT91_PMC_MDIV) ?
|
|
freq / ((mckr & AT91_PMC_MDIV) >> 7) : freq; /* mdiv ; (x >> 7) = ((x >> 8) * 2) */
|
|
if (mckr & AT91_PMC_PDIV)
|
|
freq /= 2; /* processor clock division */
|
|
} else if (cpu_has_mdiv3()) {
|
|
mck.rate_hz = (mckr & AT91_PMC_MDIV) == AT91SAM9_PMC_MDIV_3 ?
|
|
freq / 3 : freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
|
|
} else {
|
|
mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
|
|
}
|
|
|
|
if (cpu_has_alt_prescaler()) {
|
|
/* Programmable clocks can use MCK */
|
|
mck.type |= CLK_TYPE_PRIMARY;
|
|
mck.id = 4;
|
|
}
|
|
|
|
if (cpu_has_dual_matrix()) {
|
|
at91_clk_add(&h32mx_clk);
|
|
h32mx_clk.rate_hz = h32mx_clk.parent->rate_hz;
|
|
h32mx_clk.rate_hz /= (1 << ((mckr & AT91_PMC_H32MXDIV) >> 24)); /* H32MX divisor by 2 */
|
|
}
|
|
|
|
cpu_freq = freq;
|
|
|
|
/* Register the PMC's standard clocks */
|
|
for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++)
|
|
at91_clk_add(standard_pmc_clocks[i]);
|
|
|
|
if (cpu_has_pllb())
|
|
at91_clk_add(&pllb);
|
|
|
|
if (cpu_has_uhp())
|
|
at91_clk_add(&uhpck);
|
|
|
|
if (cpu_has_udpfs())
|
|
at91_clk_add(&udpck);
|
|
|
|
if (cpu_has_utmi())
|
|
at91_clk_add(&utmi_clk);
|
|
|
|
/* MCK and CPU clock are "always on" */
|
|
clk_enable(&mck);
|
|
if (cpu_has_dual_matrix())
|
|
clk_enable(&h32mx_clk);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int at91_clock_display(void)
|
|
{
|
|
if (pll_overclock)
|
|
pr_info("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000);
|
|
|
|
pr_info("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n",
|
|
cpu_freq / 1000000, (unsigned) mck.rate_hz / 1000000,
|
|
(unsigned) main_clk.rate_hz / 1000000,
|
|
((unsigned) main_clk.rate_hz % 1000000) / 1000);
|
|
|
|
return 0;
|
|
}
|
|
postconsole_initcall(at91_clock_display);
|
|
|
|
/*
|
|
* Several unused clocks may be active. Turn them off.
|
|
*/
|
|
static int at91_clock_reset(void)
|
|
{
|
|
unsigned long pcdr = 0;
|
|
unsigned long pcdr1 = 0;
|
|
unsigned long scdr = 0;
|
|
struct clk *clk;
|
|
|
|
list_for_each_entry(clk, &clocks, node) {
|
|
if (clk->users > 0)
|
|
continue;
|
|
|
|
if (clk->mode == pmc_periph_mode) {
|
|
if (cpu_has_pcr()) {
|
|
u32 pmc_mask = 1 << (clk->pid % 32);
|
|
|
|
if (clk->pid > 31)
|
|
pcdr1 |= pmc_mask;
|
|
else
|
|
pcdr |= pmc_mask;
|
|
} else
|
|
pcdr |= clk->pmc_mask;
|
|
}
|
|
|
|
if (clk->mode == pmc_sys_mode)
|
|
scdr |= clk->pmc_mask;
|
|
|
|
pr_debug("Clocks: disable unused %s\n", clk->name);
|
|
}
|
|
|
|
at91_pmc_write(AT91_PMC_PCDR, pcdr);
|
|
if (cpu_has_pcr())
|
|
at91_pmc_write(AT91_PMC_PCDR1, pcdr1);
|
|
at91_pmc_write(AT91_PMC_SCDR, scdr);
|
|
|
|
return 0;
|
|
}
|
|
late_initcall(at91_clock_reset);
|
|
|
|
#ifdef CONFIG_CMD_AT91CLK
|
|
static int do_at91clk(int argc, char *argv[])
|
|
{
|
|
u32 scsr, pcsr, pcsr1 = 0, uckr = 0, sr;
|
|
struct clk *clk;
|
|
|
|
scsr = at91_pmc_read(AT91_PMC_SCSR);
|
|
pcsr = at91_pmc_read(AT91_PMC_PCSR);
|
|
if (cpu_has_pcr())
|
|
pcsr1 = at91_pmc_read(AT91_PMC_PCSR1);
|
|
sr = at91_pmc_read(AT91_PMC_SR);
|
|
printf("SCSR = %8x\n", scsr);
|
|
printf("PCSR = %8x\n", pcsr);
|
|
if (cpu_has_pcr())
|
|
printf("PCSR1 = %8x\n", pcsr1);
|
|
printf("MOR = %8x\n", at91_pmc_read(AT91_CKGR_MOR));
|
|
printf("MCFR = %8x\n", at91_pmc_read(AT91_CKGR_MCFR));
|
|
printf("PLLA = %8x\n", at91_pmc_read(AT91_CKGR_PLLAR));
|
|
if (cpu_has_pllb())
|
|
printf("PLLB = %8x\n", at91_pmc_read(AT91_CKGR_PLLBR));
|
|
if (cpu_has_utmi()) {
|
|
uckr = at91_pmc_read(AT91_CKGR_UCKR);
|
|
printf("UCKR = %8x\n", uckr);
|
|
}
|
|
printf("MCKR = %8x\n", at91_pmc_read(AT91_PMC_MCKR));
|
|
if (cpu_has_upll())
|
|
printf("USB = %8x\n", at91_pmc_read(AT91_PMC_USB));
|
|
printf("SR = %8x\n", sr);
|
|
|
|
printf("\n");
|
|
|
|
list_for_each_entry(clk, &clocks, node) {
|
|
char *state;
|
|
char *mode = "";
|
|
|
|
if (clk->mode == pmc_sys_mode) {
|
|
state = (scsr & clk->pmc_mask) ? "on" : "off";
|
|
mode = "sys";
|
|
} else if (clk->mode == pmc_periph_mode) {
|
|
if (cpu_has_pcr()) {
|
|
u32 pmc_mask = 1 << (clk->pid % 32);
|
|
|
|
if (clk->pid > 31)
|
|
state = (pcsr1 & pmc_mask) ? "on" : "off";
|
|
else
|
|
state = (pcsr & pmc_mask) ? "on" : "off";
|
|
} else {
|
|
state = (pcsr & clk->pmc_mask) ? "on" : "off";
|
|
}
|
|
mode = "periph";
|
|
} else if (clk->mode == pmc_uckr_mode) {
|
|
state = (uckr & clk->pmc_mask) ? "on" : "off";
|
|
mode = "uckr";
|
|
} else if (clk->pmc_mask) {
|
|
state = (sr & clk->pmc_mask) ? "on" : "off";
|
|
} else if (clk == &clk32k || clk == &main_clk) {
|
|
state = "on";
|
|
} else {
|
|
state = "";
|
|
}
|
|
|
|
printf("%-10s %-7s users=%2d %-3s %10lu Hz %s\n",
|
|
clk->name, mode, clk->users, state, clk_get_rate(clk),
|
|
clk->parent ? clk->parent->name : "");
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
BAREBOX_CMD_START(at91clk)
|
|
.cmd = do_at91clk,
|
|
BAREBOX_CMD_DESC("list clock configuration")
|
|
BAREBOX_CMD_GROUP(CMD_GRP_INFO)
|
|
BAREBOX_CMD_COMPLETE(empty_complete)
|
|
BAREBOX_CMD_END
|
|
#endif
|