Also activate in defconfig. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
261 lines
5.5 KiB
C
261 lines
5.5 KiB
C
/*
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* Copyright (C) 2013-2014 Lucas Stach <l.stach@pengutronix.de>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**
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* @file
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* @brief Device driver for the Tegra 20 power management controller.
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*/
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#include <command.h>
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#include <common.h>
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#include <init.h>
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#include <io.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/reset.h>
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#include <mach/lowlevel.h>
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#include <mach/tegra-powergate.h>
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#include <reset_source.h>
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#include <mach/tegra20-pmc.h>
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static void __iomem *pmc_base;
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static int tegra_num_powerdomains;
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/* main SoC reset trigger */
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void __noreturn reset_cpu(ulong addr)
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{
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writel(PMC_CNTRL_MAIN_RST, pmc_base + PMC_CNTRL);
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unreachable();
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}
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EXPORT_SYMBOL(reset_cpu);
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static int tegra_powergate_set(int id, bool new_state)
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{
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bool status;
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status = readl(pmc_base + PMC_PWRGATE_STATUS) & (1 << id);
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if (status == new_state) {
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return 0;
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}
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writel(PMC_PWRGATE_TOGGLE_START | id, pmc_base + PMC_PWRGATE_TOGGLE);
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/* I don't know exactly why this is needed, seems to flush the write */
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readl(pmc_base + PMC_PWRGATE_TOGGLE);
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return 0;
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}
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int tegra_powergate_power_on(int id)
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{
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if (id < 0 || id >= tegra_num_powerdomains)
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return -EINVAL;
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return tegra_powergate_set(id, true);
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}
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int tegra_powergate_power_off(int id)
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{
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if (id < 0 || id >= tegra_num_powerdomains)
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return -EINVAL;
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return tegra_powergate_set(id, false);
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}
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EXPORT_SYMBOL(tegra_powergate_power_off);
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int tegra_powergate_is_powered(int id)
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{
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u32 status;
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if (id < 0 || id >= tegra_num_powerdomains)
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return -EINVAL;
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status = readl(pmc_base + PMC_PWRGATE_STATUS) & (1 << id);
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return !!status;
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}
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int tegra_powergate_remove_clamping(int id)
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{
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u32 mask;
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if (id < 0 || id >= tegra_num_powerdomains)
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return -EINVAL;
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/*
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* Tegra 2 has a bug where PCIE and VDE clamping masks are
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* swapped relatively to the partition ids
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*/
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if (id == TEGRA_POWERGATE_VDEC)
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mask = (1 << TEGRA_POWERGATE_PCIE);
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else if (id == TEGRA_POWERGATE_PCIE)
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mask = (1 << TEGRA_POWERGATE_VDEC);
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else
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mask = (1 << id);
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writel(mask, pmc_base + PMC_REMOVE_CLAMPING_CMD);
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return 0;
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}
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EXPORT_SYMBOL(tegra_powergate_remove_clamping);
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/* Must be called with clk disabled, and returns with clk enabled */
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int tegra_powergate_sequence_power_up(int id, struct clk *clk,
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struct reset_control *rst)
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{
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int ret;
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reset_control_assert(rst);
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ret = tegra_powergate_power_on(id);
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if (ret)
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goto err_power;
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ret = clk_enable(clk);
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if (ret)
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goto err_clk;
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udelay(10);
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ret = tegra_powergate_remove_clamping(id);
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if (ret)
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goto err_clamp;
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udelay(10);
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reset_control_deassert(rst);
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return 0;
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err_clamp:
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clk_disable(clk);
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err_clk:
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tegra_powergate_power_off(id);
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err_power:
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return ret;
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}
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EXPORT_SYMBOL(tegra_powergate_sequence_power_up);
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static int tegra_powergate_init(void)
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{
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switch (tegra_get_chiptype()) {
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case TEGRA20:
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tegra_num_powerdomains = 7;
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break;
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case TEGRA30:
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tegra_num_powerdomains = 14;
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break;
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case TEGRA114:
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tegra_num_powerdomains = 23;
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break;
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case TEGRA124:
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tegra_num_powerdomains = 25;
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break;
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default:
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/* Unknown Tegra variant. Disable powergating */
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tegra_num_powerdomains = 0;
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break;
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}
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return 0;
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}
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static void tegra20_pmc_detect_reset_cause(void)
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{
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u32 reg = readl(pmc_base + PMC_RST_STATUS);
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switch ((reg & PMC_RST_STATUS_RST_SRC_MASK) >>
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PMC_RST_STATUS_RST_SRC_SHIFT) {
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case PMC_RST_STATUS_RST_SRC_POR:
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reset_source_set(RESET_POR);
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break;
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case PMC_RST_STATUS_RST_SRC_WATCHDOG:
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reset_source_set(RESET_WDG);
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break;
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case PMC_RST_STATUS_RST_SRC_LP0:
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reset_source_set(RESET_WKE);
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break;
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case PMC_RST_STATUS_RST_SRC_SW_MAIN:
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reset_source_set(RESET_RST);
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break;
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case PMC_RST_STATUS_RST_SRC_SENSOR:
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reset_source_set(RESET_THERM);
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break;
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default:
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reset_source_set(RESET_UKWN);
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break;
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}
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}
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static int tegra20_pmc_probe(struct device_d *dev)
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{
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pmc_base = dev_request_mem_region(dev, 0);
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if (IS_ERR(pmc_base)) {
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dev_err(dev, "could not get memory region\n");
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return PTR_ERR(pmc_base);
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}
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tegra_powergate_init();
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if (IS_ENABLED(CONFIG_RESET_SOURCE))
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tegra20_pmc_detect_reset_cause();
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return 0;
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}
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static int do_tegrarcm(int argc, char *argv[])
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{
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writel(2, pmc_base + PMC_SCRATCH(0));
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reset_cpu(0);
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return 0;
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}
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static __maybe_unused struct of_device_id tegra20_pmc_dt_ids[] = {
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{
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.compatible = "nvidia,tegra20-pmc",
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}, {
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.compatible = "nvidia,tegra30-pmc",
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}, {
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.compatible = "nvidia,tegra124-pmc",
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}, {
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/* sentinel */
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}
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};
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static struct driver_d tegra20_pmc_driver = {
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.probe = tegra20_pmc_probe,
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.name = "tegra20-pmc",
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.of_compatible = DRV_OF_COMPAT(tegra20_pmc_dt_ids),
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};
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static int tegra20_pmc_init(void)
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{
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return platform_driver_register(&tegra20_pmc_driver);
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}
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coredevice_initcall(tegra20_pmc_init);
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BAREBOX_CMD_HELP_START(tegrarcm)
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BAREBOX_CMD_HELP_TEXT("Get into recovery mode without using a physical switch\n")
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BAREBOX_CMD_HELP_END
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BAREBOX_CMD_START(tegrarcm)
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.cmd = do_tegrarcm,
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BAREBOX_CMD_DESC("Usage: tegrarcm")
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BAREBOX_CMD_GROUP(CMD_GRP_HWMANIP)
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BAREBOX_CMD_HELP(cmd_tegrarcm_help)
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BAREBOX_CMD_END
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