d8753571b2
This file originates in Linux. Linux has it under include/linux/ directory since commit dccd2304cc90. Let's move it to the same place as well in barebox. This commit was generated by the following commands: find -name '*.[chS]' | xargs sed -i -e 's:<sizes.h>:<linux/sizes.h>:' git mv include/sizes.h include/linux/ Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
85 lines
2.2 KiB
C
85 lines
2.2 KiB
C
/*
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* Copyright (C) 2013-2014 Lucas Stach <l.stach@pengutronix.de>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <common.h>
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#include <linux/sizes.h>
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#include <asm/barebox-arm-head.h>
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#include <asm/barebox-arm.h>
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#include <asm/errata.h>
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#include <mach/lowlevel.h>
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#include <mach/tegra20-pmc.h>
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#include <mach/tegra20-car.h>
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void tegra_maincomplex_entry(void)
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{
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uint32_t rambase, ramsize;
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enum tegra_chiptype chiptype;
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u32 reg = 0;
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arm_cpu_lowlevel_init();
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chiptype = tegra_get_chiptype();
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/* enable ARM errata workarounds early */
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switch (chiptype) {
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case TEGRA20:
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enable_arm_errata_716044_war();
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enable_arm_errata_742230_war();
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enable_arm_errata_751472_war();
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break;
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case TEGRA30:
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enable_arm_errata_743622_war();
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enable_arm_errata_751472_war();
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break;
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default:
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break;
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}
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/* switch to PLLX */
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writel(CRC_CCLK_BURST_POLICY_SYS_STATE_RUN <<
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CRC_CCLK_BURST_POLICY_SYS_STATE_SHIFT |
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CRC_CCLK_BURST_POLICY_SRC_PLLX_OUT0 <<
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CRC_CCLK_BURST_POLICY_RUN_SRC_SHIFT,
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TEGRA_CLK_RESET_BASE + CRC_CCLK_BURST_POLICY);
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writel(CRC_SUPER_CDIV_ENB, TEGRA_CLK_RESET_BASE + CRC_SUPER_CCLK_DIV);
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if (chiptype >= TEGRA114) {
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asm("mrc p15, 1, %0, c9, c0, 2" : : "r" (reg));
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reg &= ~7;
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reg |= 2;
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asm("mcr p15, 1, %0, c9, c0, 2" : : "r" (reg));
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}
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switch (chiptype) {
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case TEGRA20:
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rambase = 0x0;
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ramsize = tegra20_get_ramsize();
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break;
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case TEGRA30:
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case TEGRA124:
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rambase = SZ_2G;
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ramsize = tegra30_get_ramsize();
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break;
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default:
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/* If we don't know the chiptype, better bail out */
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unreachable();
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}
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barebox_arm_entry(rambase, ramsize,
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(void *)readl(TEGRA_PMC_BASE + PMC_SCRATCH(10)));
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}
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