068bed22a6
With multiboard support the compiletime generated BOARDINFO string gets more and more meaningless. This removes it from Kconfig and replaces it with a variable that can be set at boardlevel. Also many boards have a standard setting for the hostname in the environment. This patch also moves the standard to C code by calling barebox_set_hostname(). Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
126 lines
3.2 KiB
C
126 lines
3.2 KiB
C
/*
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* Copyright
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* (C) 2013 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <common.h>
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#include <init.h>
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#include <io.h>
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#include <ns16550.h>
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#include <linux/clk.h>
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#include <linux/clkdev.h>
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#include <asm/memory.h>
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#include <mach/armada-370-xp-regs.h>
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#define CONSOLE_UART_BASE \
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ARMADA_370_XP_UARTn_BASE(CONFIG_MVEBU_CONSOLE_UART)
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static struct clk *tclk;
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static inline void armada_370_xp_memory_find(unsigned long *phys_base,
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unsigned long *phys_size)
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{
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int cs;
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*phys_base = ~0;
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*phys_size = 0;
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for (cs = 0; cs < 4; cs++) {
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u32 base = readl(ARMADA_370_XP_SDRAM_BASE + DDR_BASE_CSn(cs));
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u32 ctrl = readl(ARMADA_370_XP_SDRAM_BASE + DDR_SIZE_CSn(cs));
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/* Skip non-enabled CS */
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if ((ctrl & DDR_SIZE_ENABLED) != DDR_SIZE_ENABLED)
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continue;
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base &= DDR_BASE_CS_LOW_MASK;
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if (base < *phys_base)
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*phys_base = base;
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*phys_size += (ctrl | ~DDR_SIZE_MASK) + 1;
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}
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}
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static struct NS16550_plat uart_plat = {
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.shift = 2,
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};
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static int armada_370_xp_add_uart(void)
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{
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uart_plat.clock = clk_get_rate(tclk);
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if (!add_ns16550_device(DEVICE_ID_DYNAMIC,
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(unsigned int)CONSOLE_UART_BASE, 32,
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IORESOURCE_MEM_32BIT, &uart_plat))
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return -ENODEV;
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return 0;
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}
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#if defined(CONFIG_ARCH_ARMADA_370)
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static int armada_370_init_clocks(void)
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{
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u32 val = readl(ARMADA_370_XP_SAR_BASE + SAR_LOW);
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unsigned int rate;
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/*
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* On Armada 370, the TCLK frequency can be either
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* 166 Mhz or 200 Mhz
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*/
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if ((val & SAR_TCLK_FREQ) == SAR_TCLK_FREQ)
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rate = 200000000;
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else
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rate = 166000000;
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tclk = clk_fixed("tclk", rate);
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return clk_register_clkdev(tclk, NULL, "mvebu-timer");
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}
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#define armada_370_xp_init_clocks() armada_370_init_clocks()
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#endif
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#if defined(CONFIG_ARCH_ARMADA_XP)
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static int armada_xp_init_clocks(void)
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{
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/* On Armada XP, the TCLK frequency is always 250 Mhz */
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tclk = clk_fixed("tclk", 250000000);
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return 0;
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}
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#define armada_370_xp_init_clocks() armada_xp_init_clocks()
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#endif
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static int armada_370_xp_init_soc(void)
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{
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unsigned long phys_base, phys_size;
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barebox_set_model("Marvell Armada 370/XP");
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barebox_set_hostname("armada");
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armada_370_xp_init_clocks();
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clkdev_add_physbase(tclk, (unsigned int)ARMADA_370_XP_TIMER_BASE, NULL);
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add_generic_device("mvebu-timer", DEVICE_ID_SINGLE, NULL,
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(unsigned int)ARMADA_370_XP_TIMER_BASE, 0x30,
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IORESOURCE_MEM, NULL);
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armada_370_xp_memory_find(&phys_base, &phys_size);
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arm_add_mem_device("ram0", phys_base, phys_size);
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armada_370_xp_add_uart();
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return 0;
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}
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core_initcall(armada_370_xp_init_soc);
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void __noreturn reset_cpu(unsigned long addr)
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{
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writel(0x1, ARMADA_370_XP_SYSCTL_BASE + 0x60);
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writel(0x1, ARMADA_370_XP_SYSCTL_BASE + 0x64);
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while (1)
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;
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}
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EXPORT_SYMBOL(reset_cpu);
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