831 lines
22 KiB
C
831 lines
22 KiB
C
/*
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* i.MX6 DDR controller calibration functions
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* Based on Freescale code
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*
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* Copyright (C) 2013 Sascha Hauer <s.hauer@pengutronix.de>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <common.h>
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#include <io.h>
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#include <mach/imx6-mmdc.h>
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int mmdc_do_write_level_calibration(void)
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{
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u32 esdmisc_val, zq_val;
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int errorcount = 0;
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u32 val;
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u32 ddr_mr1 = 0x4;
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/* disable DDR logic power down timer */
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val = readl((P0_IPS + MDPDC));
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val &= 0xffff00ff;
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writel(val, (P0_IPS + MDPDC)),
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/* disable Adopt power down timer */
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val = readl((P0_IPS + MAPSR));
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val |= 0x1;
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writel(val, (P0_IPS + MAPSR));
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pr_debug("Start write leveling calibration \n");
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/*
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* disable auto refresh and ZQ calibration
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* before proceeding with Write Leveling calibration
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*/
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esdmisc_val = readl(P0_IPS + MDREF);
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writel(0x0000C000, (P0_IPS + MDREF));
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zq_val = readl(P0_IPS + MPZQHWCTRL);
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writel(zq_val & ~(0x3), (P0_IPS + MPZQHWCTRL));
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/*
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* Configure the external DDR device to enter write leveling mode
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* through Load Mode Register command
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* Register setting:
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* Bits[31:16] MR1 value (0x0080 write leveling enable)
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* Bit[9] set WL_EN to enable MMDC DQS output
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* Bits[6:4] set CMD bits for Load Mode Register programming
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* Bits[2:0] set CMD_BA to 0x1 for DDR MR1 programming
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*/
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writel(0x00808231, P0_IPS + MDSCR);
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/* Activate automatic calibration by setting MPWLGCR[HW_WL_EN] */
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writel(0x00000001, P0_IPS + MPWLGCR);
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/* Upon completion of this process the MMDC de-asserts the MPWLGCR[HW_WL_EN] */
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while (readl(P0_IPS + MPWLGCR) & 0x00000001);
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/* check for any errors: check both PHYs for x64 configuration, if x32, check only PHY0 */
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if ((readl(P0_IPS + MPWLGCR) & 0x00000F00) ||
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(readl(P1_IPS + MPWLGCR) & 0x00000F00)) {
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errorcount++;
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}
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pr_debug("Write leveling calibration completed\n");
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/*
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* User should issue MRS command to exit write leveling mode
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* through Load Mode Register command
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* Register setting:
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* Bits[31:16] MR1 value "ddr_mr1" value from initialization
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* Bit[9] clear WL_EN to disable MMDC DQS output
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* Bits[6:4] set CMD bits for Load Mode Register programming
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* Bits[2:0] set CMD_BA to 0x1 for DDR MR1 programming
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*/
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writel(((ddr_mr1 << 16)+0x8031), P0_IPS + MDSCR);
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/* re-enable to auto refresh and zq cal */
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writel(esdmisc_val, (P0_IPS + MDREF));
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writel(zq_val, (P0_IPS + MPZQHWCTRL));
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pr_debug("MMDC_MPWLDECTRL0 after write level cal: 0x%08X\n",
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readl(P0_IPS + MPWLDECTRL0));
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pr_debug("MMDC_MPWLDECTRL1 after write level cal: 0x%08X\n",
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readl(P0_IPS + MPWLDECTRL1));
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pr_debug("MMDC_MPWLDECTRL0 after write level cal: 0x%08X\n",
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readl(P1_IPS + MPWLDECTRL0));
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pr_debug("MMDC_MPWLDECTRL1 after write level cal: 0x%08X\n",
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readl(P1_IPS + MPWLDECTRL1));
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/* enable DDR logic power down timer */
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val = readl((P0_IPS + MDPDC));
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val |= 0x00005500;
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writel(val, (P0_IPS + MDPDC));
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/* enable Adopt power down timer: */
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val = readl(P0_IPS + MAPSR);
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val &= 0xfffffff7;
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writel(val, (P0_IPS + MAPSR));
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/* clear CON_REQ */
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writel(0, (P0_IPS + MDSCR));
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return 0;
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}
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static void modify_dg_result(void __iomem *reg_st0, void __iomem *reg_st1,
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void __iomem *reg_ctrl)
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{
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u32 dg_tmp_val, dg_dl_abs_offset, dg_hc_del, val_ctrl;
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/*
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* DQS gating absolute offset should be modified from reflecting (HW_DG_LOWx + HW_DG_UPx)/2
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* to reflecting (HW_DG_UPx - 0x80)
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*/
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val_ctrl = readl(reg_ctrl);
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val_ctrl &= 0xf0000000;
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dg_tmp_val = ((readl(reg_st0) & 0x07ff0000) >> 16) - 0xc0;
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dg_dl_abs_offset = dg_tmp_val & 0x7f;
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dg_hc_del = (dg_tmp_val & 0x780) << 1;
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val_ctrl |= dg_dl_abs_offset + dg_hc_del;
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dg_tmp_val = ((readl(reg_st1) & 0x07ff0000) >> 16) - 0xc0;
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dg_dl_abs_offset = dg_tmp_val & 0x7f;
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dg_hc_del = (dg_tmp_val & 0x780) << 1;
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val_ctrl |= (dg_dl_abs_offset + dg_hc_del) << 16;
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writel(val_ctrl, reg_ctrl);
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}
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static void mmdc_precharge_all(int cs0_enable, int cs1_enable)
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{
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/*
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* Issue the Precharge-All command to the DDR device for both chip selects
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* Note, CON_REQ bit should also remain set
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* If only using one chip select, then precharge only the desired chip select
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*/
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if (cs0_enable)
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writel(0x04008050, P0_IPS + MDSCR);
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if (cs1_enable)
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writel(0x04008058, P0_IPS + MDSCR);
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}
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static void mmdc_force_delay_measurement(int data_bus_size)
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{
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writel(0x800, P0_IPS + MPMUR);
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if (data_bus_size == 0x2)
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writel(0x800, P1_IPS + MPMUR);
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}
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static void mmdc_reset_read_data_fifos(void)
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{
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uint32_t v;
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/*
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* Reset the read data FIFOs (two resets); only need to issue reset to PHY0 since in x64
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* mode, the reset will also go to PHY1
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* read data FIFOs reset1
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*/
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v = readl(P0_IPS + MPDGCTRL0);
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v |= 0x80000000;
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writel(v, P0_IPS + MPDGCTRL0);
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while (readl((P0_IPS + MPDGCTRL0)) & 0x80000000);
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/* read data FIFOs reset2 */
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v = readl(P0_IPS + MPDGCTRL0);
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v |= 0x80000000;
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writel(v, P0_IPS + MPDGCTRL0);
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while (readl((P0_IPS + MPDGCTRL0)) & 0x80000000);
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}
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int mmdc_do_dqs_calibration(void)
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{
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u32 esdmisc_val, v;
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int g_error_write_cal;
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int temp_ref;
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int cs0_enable_initial;
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int cs1_enable_initial;
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int PDDWord = 0x00ffff00;
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int errorcount = 0;
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int cs0_enable;
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int cs1_enable;
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int data_bus_size;
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/* check to see which chip selects are enabled */
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cs0_enable_initial = (readl(P0_IPS + MDCTL) & 0x80000000) >> 31;
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cs1_enable_initial = (readl(P0_IPS + MDCTL) & 0x40000000) >> 30;
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/* disable DDR logic power down timer */
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v = readl(P0_IPS + MDPDC);
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v &= ~0xff00;
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writel(v, P0_IPS + MDPDC);
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/* disable Adopt power down timer */
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v = readl(P0_IPS + MAPSR);
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v |= 0x1;
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writel(v, P0_IPS + MAPSR);
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/* set DQS pull ups */
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v = readl(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0) | 0x7000;
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writel(v, IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0);
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v = readl(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1) | 0x7000;
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writel(v, IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1);
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v = readl(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2) | 0x7000;
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writel(v, IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2);
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v = readl(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3) | 0x7000;
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writel(v, IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3);
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v = readl(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4) | 0x7000;
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writel(v, IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4);
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v = readl(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5) | 0x7000;
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writel(v, IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5);
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v = readl(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6) | 0x7000;
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writel(v, IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6);
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v = readl(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7) | 0x7000;
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writel(v, IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7);
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esdmisc_val = readl(P0_IPS + MDMISC);
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/* set RALAT and WALAT to max */
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v = readl(P0_IPS + MDMISC);
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v |= (1 << 6) | (1 << 7) | (1 << 8) | (1 << 16) | (1 << 17);
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writel(v, P0_IPS + MDMISC);
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/*
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* disable auto refresh
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* before proceeding with calibration
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*/
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temp_ref = readl(P0_IPS + MDREF);
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writel(0x0000C000, P0_IPS + MDREF);
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/*
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* per the ref manual, issue one refresh cycle MDSCR[CMD]= 0x2,
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* this also sets the CON_REQ bit.
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*/
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if (cs0_enable_initial)
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writel(0x00008020, P0_IPS + MDSCR);
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if (cs1_enable_initial)
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writel(0x00008028, P0_IPS + MDSCR);
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/* poll to make sure the con_ack bit was asserted */
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while (!(readl(P0_IPS + MDSCR) & 0x00004000)) ;
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/*
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* check MDMISC register CALIB_PER_CS to see which CS calibration is
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* targeted to (under normal cases, it should be cleared as this is the
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* default value, indicating calibration is directed to CS0). Disable
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* the other chip select not being target for calibration to avoid any
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* potential issues This will get re-enabled at end of calibration.
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*/
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v = readl(P0_IPS + MDCTL);
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if ((readl(P0_IPS + MDMISC) & 0x00100000) == 0)
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v &= ~(1 << 30); /* clear SDE_1 */
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else
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v &= ~(1 << 31); /* clear SDE_0 */
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writel(v, P0_IPS + MDCTL);
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/*
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* check to see which chip selects are now enabled for the remainder
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* of the calibration.
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*/
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cs0_enable = (readl(P0_IPS + MDCTL) & 0x80000000) >> 31;
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cs1_enable = (readl(P0_IPS + MDCTL) & 0x40000000) >> 30;
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/* check to see what is the data bus size */
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data_bus_size = (readl(P0_IPS + MDCTL) & 0x30000) >> 16;
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mmdc_precharge_all(cs0_enable, cs1_enable);
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/* Write the pre-defined value into MPPDCMPR1 */
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writel(PDDWord, P0_IPS + MPPDCMPR1);
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/*
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* Issue a write access to the external DDR device by setting the bit SW_DUMMY_WR (bit 0)
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* in the MPSWDAR0 and then poll this bit until it clears to indicate completion of the
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* write access.
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*/
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v = readl(P0_IPS + MPSWDAR);
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v |= (1 << 0);
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writel(v, P0_IPS + MPSWDAR);
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while (readl(P0_IPS + MPSWDAR) & 0x00000001);
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/*
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* Set the RD_DL_ABS# bits to their default values (will be calibrated later in
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* the read delay-line calibration)
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* Both PHYs for x64 configuration, if x32, do only PHY0
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*/
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writel(0x40404040, P0_IPS + MPRDDLCTL);
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if (data_bus_size == 0x2)
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writel(0x40404040, P1_IPS + MPRDDLCTL);
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/* Force a measurement, for previous delay setup to take effect */
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mmdc_force_delay_measurement(data_bus_size);
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/*
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* Read DQS Gating calibration
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*/
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pr_debug("Starting DQS gating calibration...\n");
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mmdc_reset_read_data_fifos();
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/*
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* Start the automatic read DQS gating calibration process by asserting
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* MPDGCTRL0[HW_DG_EN] and MPDGCTRL0[DG_CMP_CYC] and then poll
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* MPDGCTRL0[HW_DG_EN]] until this bit clears to indicate completion.
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* Also, ensure that MPDGCTRL0[HW_DG_ERR] is clear to indicate no errors
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* were seen during calibration. Set bit 30: chooses option to wait 32
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* cycles instead of 16 before comparing read data
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*/
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v = readl(P0_IPS + MPDGCTRL0);
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v |= (1 << 30);
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writel(v, P0_IPS + MPDGCTRL0);
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/* Set bit 28 to start automatic read DQS gating calibration */
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v |= (1 << 28);
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writel(v, P0_IPS + MPDGCTRL0);
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/*
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* Poll for completion
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* MPDGCTRL0[HW_DG_EN] should be 0
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*/
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while (readl(P0_IPS + MPDGCTRL0) & 0x10000000);
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/*
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* Check to see if any errors were encountered during calibration
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* (check MPDGCTRL0[HW_DG_ERR])
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* check both PHYs for x64 configuration, if x32, check only PHY0
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*/
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if (data_bus_size == 0x2) {
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if ((readl(P0_IPS + MPDGCTRL0) & 0x00001000) ||
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(readl(P1_IPS + MPDGCTRL0) & 0x00001000))
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errorcount++;
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} else {
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if (readl(P0_IPS + MPDGCTRL0) & 0x00001000)
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errorcount++;
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}
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/*
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* DQS gating absolute offset should be modified from reflecting
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* (HW_DG_LOWx + HW_DG_UPx)/2 to reflecting (HW_DG_UPx - 0x80)
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*/
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modify_dg_result(P0_IPS + MPDGHWST0,
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P0_IPS + MPDGHWST1,
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P0_IPS + MPDGCTRL0);
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modify_dg_result(P0_IPS + MPDGHWST2,
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P0_IPS + MPDGHWST3,
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P0_IPS + MPDGCTRL1);
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if (data_bus_size == 0x2) {
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modify_dg_result(P1_IPS + MPDGHWST0,
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P1_IPS + MPDGHWST1,
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P1_IPS + MPDGCTRL0);
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modify_dg_result(P1_IPS + MPDGHWST2,
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P1_IPS + MPDGHWST3,
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P1_IPS + MPDGCTRL1);
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}
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pr_debug("DQS gating calibration completed.\n");
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/*
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* Read delay Calibration
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*/
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pr_debug("Starting read calibration...\n");
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mmdc_reset_read_data_fifos();
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mmdc_precharge_all(cs0_enable, cs1_enable);
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/*
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* Read delay-line calibration
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* Start the automatic read calibration process by asserting MPRDDLHWCTL[ HW_RD_DL_EN]
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*/
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writel(0x00000030, P0_IPS + MPRDDLHWCTL);
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/*
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* poll for completion
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* MMDC indicates that the write data calibration had finished by setting
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* MPRDDLHWCTL[HW_RD_DL_EN] = 0
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* Also, ensure that no error bits were set
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*/
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while (readl(P0_IPS + MPRDDLHWCTL) & 0x00000010) ;
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/* check both PHYs for x64 configuration, if x32, check only PHY0 */
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if (data_bus_size == 0x2) {
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if ((readl(P0_IPS + MPRDDLHWCTL) & 0x0000000f) ||
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(readl(P1_IPS + MPRDDLHWCTL) & 0x0000000f)) {
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errorcount++;
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}
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} else {
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if (readl(P0_IPS + MPRDDLHWCTL) & 0x0000000f) {
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errorcount++;
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}
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}
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pr_debug("Read calibration completed\n");
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/*
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* Write delay Calibration
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*/
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pr_debug("Starting write calibration...\n");
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mmdc_reset_read_data_fifos();
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mmdc_precharge_all(cs0_enable, cs1_enable);
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/*
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* Set the WR_DL_ABS# bits to their default values
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* Both PHYs for x64 configuration, if x32, do only PHY0
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*/
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writel(0x40404040, P0_IPS + MPWRDLCTL);
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if (data_bus_size == 0x2)
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writel(0x40404040, P1_IPS + MPWRDLCTL);
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mmdc_force_delay_measurement(data_bus_size);
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/* Start the automatic write calibration process by asserting MPWRDLHWCTL0[HW_WR_DL_EN] */
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writel(0x00000030, P0_IPS + MPWRDLHWCTL);
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/*
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* poll for completion
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* MMDC indicates that the write data calibration had finished by setting
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* MPWRDLHWCTL[HW_WR_DL_EN] = 0
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* Also, ensure that no error bits were set
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*/
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while (readl(P0_IPS + MPWRDLHWCTL) & 0x00000010) ;
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/* check both PHYs for x64 configuration, if x32, check only PHY0 */
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if (data_bus_size == 0x2) {
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if ((readl(P0_IPS + MPWRDLHWCTL) & 0x0000000f) ||
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(readl(P1_IPS + MPWRDLHWCTL) & 0x0000000f)) {
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errorcount++;
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g_error_write_cal = 1; // set the g_error_write_cal
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}
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} else {
|
|
if (readl(P0_IPS + MPWRDLHWCTL) & 0x0000000f) {
|
|
errorcount++;
|
|
g_error_write_cal = 1; // set the g_error_write_cal
|
|
}
|
|
}
|
|
|
|
pr_debug("Write calibration completed\n");
|
|
|
|
mmdc_reset_read_data_fifos();
|
|
|
|
pr_debug("\n");
|
|
|
|
/* enable DDR logic power down timer */
|
|
v = readl(P0_IPS + MDPDC) | 0x00005500;
|
|
writel(v, P0_IPS + MDPDC);
|
|
|
|
/* enable Adopt power down timer */
|
|
v = readl(P0_IPS + MAPSR) & 0xfffffff7;
|
|
writel(v, P0_IPS + MAPSR);
|
|
|
|
/* restore MDMISC value (RALAT, WALAT) */
|
|
writel(esdmisc_val, P1_IPS + MDMISC);
|
|
|
|
/* clear DQS pull ups */
|
|
v = readl(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0) & ~0x7000;
|
|
writel(v, IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0);
|
|
v = readl(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1) & ~0x7000;
|
|
writel(v, IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1);
|
|
v = readl(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2) & ~0x7000;
|
|
writel(v, IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2);
|
|
v = readl(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3) & ~0x7000;
|
|
writel(v, IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3);
|
|
v = readl(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4) & ~0x7000;
|
|
writel(v, IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4);
|
|
v = readl(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5) & ~0x7000;
|
|
writel(v, IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5);
|
|
v = readl(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6) & ~0x7000;
|
|
writel(v, IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6);
|
|
v = readl(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7) & ~0x7000;
|
|
writel(v, IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7);
|
|
|
|
v = readl(P0_IPS + MDCTL);
|
|
|
|
/* re-enable SDE (chip selects) if they were set initially */
|
|
if (cs1_enable_initial == 1)
|
|
v |= (1 << 30); /* set SDE_1 */
|
|
|
|
if (cs0_enable_initial == 1)
|
|
v |= (1 << 31); /* set SDE_0 */
|
|
|
|
writel(v, P0_IPS + MDCTL);
|
|
|
|
/* re-enable to auto refresh */
|
|
writel(temp_ref, P0_IPS + MDREF);
|
|
|
|
/* clear the MDSCR (including the con_req bit) */
|
|
writel(0x0, P0_IPS + MDSCR); /* CS0 */
|
|
|
|
/* poll to make sure the con_ack bit is clear */
|
|
while (readl(P0_IPS + MDSCR) & 0x00004000) ;
|
|
|
|
pr_debug("MMDC registers updated from calibration \n");
|
|
pr_debug("\nRead DQS Gating calibration\n");
|
|
pr_debug("MPDGCTRL0 PHY0 (0x021b083c) = 0x%08X\n", readl(P0_IPS + MPDGCTRL0));
|
|
pr_debug("MPDGCTRL1 PHY0 (0x021b0840) = 0x%08X\n", readl(P0_IPS + MPDGCTRL1));
|
|
pr_debug("MPDGCTRL0 PHY1 (0x021b483c) = 0x%08X\n", readl(P1_IPS + MPDGCTRL0));
|
|
pr_debug("MPDGCTRL1 PHY1 (0x021b4840) = 0x%08X\n", readl(P1_IPS + MPDGCTRL1));
|
|
pr_debug("\nRead calibration\n");
|
|
pr_debug("MPRDDLCTL PHY0 (0x021b0848) = 0x%08X\n", readl(P0_IPS + MPRDDLCTL));
|
|
pr_debug("MPRDDLCTL PHY1 (0x021b4848) = 0x%08X\n", readl(P1_IPS + MPRDDLCTL));
|
|
pr_debug("\nWrite calibration\n");
|
|
pr_debug("MPWRDLCTL PHY0 (0x021b0850) = 0x%08X\n", readl(P0_IPS + MPWRDLCTL));
|
|
pr_debug("MPWRDLCTL PHY1 (0x021b4850) = 0x%08X\n", readl(P1_IPS + MPWRDLCTL));
|
|
pr_debug("\n");
|
|
/*
|
|
* registers below are for debugging purposes
|
|
* these print out the upper and lower boundaries captured during read DQS gating calibration
|
|
*/
|
|
pr_debug("Status registers, upper and lower bounds, for read DQS gating. \n");
|
|
pr_debug("MPDGHWST0 PHY0 (0x021b087c) = 0x%08X\n", readl(P0_IPS + MPDGHWST0));
|
|
pr_debug("MPDGHWST1 PHY0 (0x021b0880) = 0x%08X\n", readl(P0_IPS + MPDGHWST1));
|
|
pr_debug("MPDGHWST2 PHY0 (0x021b0884) = 0x%08X\n", readl(P0_IPS + MPDGHWST2));
|
|
pr_debug("MPDGHWST3 PHY0 (0x021b0888) = 0x%08X\n", readl(P0_IPS + MPDGHWST3));
|
|
pr_debug("MPDGHWST0 PHY1 (0x021b487c) = 0x%08X\n", readl(P1_IPS + MPDGHWST0));
|
|
pr_debug("MPDGHWST1 PHY1 (0x021b4880) = 0x%08X\n", readl(P1_IPS + MPDGHWST1));
|
|
pr_debug("MPDGHWST2 PHY1 (0x021b4884) = 0x%08X\n", readl(P1_IPS + MPDGHWST2));
|
|
pr_debug("MPDGHWST3 PHY1 (0x021b4888) = 0x%08X\n", readl(P1_IPS + MPDGHWST3));
|
|
|
|
return errorcount;
|
|
}
|
|
|
|
#ifdef MMDC_SOFTWARE_CALIBRATION
|
|
|
|
static void mmdc_set_dqs(u32 value)
|
|
{
|
|
value |= value << 8 | value << 16 | value << 24;
|
|
|
|
writel(value, P0_IPS + MPRDDLCTL);
|
|
|
|
if (data_bus_size == 0x2)
|
|
writel(value, P1_IPS + MPRDDLCTL);
|
|
}
|
|
|
|
static void mmdc_set_wr_delay(u32 value)
|
|
{
|
|
value |= value << 8 | value << 16 | value << 24;
|
|
|
|
writel(value, P0_IPS + MPWRDLCTL);
|
|
|
|
if (data_bus_size == 0x2)
|
|
writel(value, P1_IPS + MPWRDLCTL);
|
|
}
|
|
|
|
static void mmdc_issue_write_access(void __iomem *base)
|
|
{
|
|
u32 v;
|
|
|
|
/*
|
|
* Issue a write access to the external DDR device by setting the bit SW_DUMMY_WR (bit 0)
|
|
* in the MPSWDAR0 and then poll this bit until it clears to indicate completion of the
|
|
* write access.
|
|
*/
|
|
|
|
v = readl(P0_IPS + MPSWDAR);
|
|
v |= (1 << 0);
|
|
writel(v, P0_IPS + MPSWDAR);
|
|
|
|
while (readl(P0_IPS + MPSWDAR) & 0x00000001);
|
|
}
|
|
|
|
static void mmdc_issue_read_access(void __iomem *base)
|
|
{
|
|
/*
|
|
* Issue a write access to the external DDR device by setting the bit SW_DUMMY_WR (bit 0)
|
|
* in the MPSWDAR0 and then poll this bit until it clears to indicate completion of the
|
|
* write access.
|
|
*/
|
|
|
|
v = readl(P0_IPS + MPSWDAR);
|
|
v |= (1 << 1);
|
|
writel(v, P0_IPS + MPSWDAR);
|
|
|
|
while (readl(P0_IPS + MPSWDAR) & 0x00000002);
|
|
}
|
|
|
|
static int total_lower[2] = { 0x0, 0x0 };
|
|
static int total_upper[2] = { 0xff, 0xff };
|
|
|
|
static int mmdc_is_valid(void __iomem *base, int delay, int rd)
|
|
{
|
|
u32 val;
|
|
|
|
if (rd)
|
|
mmdc_set_dqs(delay);
|
|
else
|
|
mmdc_set_wr_delay(delay);
|
|
|
|
mmdc_force_delay_measurement();
|
|
|
|
mdelay(1);
|
|
|
|
if (!rd)
|
|
mmdc_issue_write_access(base);
|
|
|
|
mmdc_issue_read_access(base);
|
|
|
|
val = readl(base + MPSWDAR);
|
|
|
|
if ((val & 0x3c) == 0x3c)
|
|
return 1;
|
|
else
|
|
return 0;
|
|
#ifdef MMDC_SOFWARE_CALIB_COMPARE_RESULTS
|
|
if ((val & 0x3c) == 0x3c) {
|
|
if (lower < 0)
|
|
lower = i;
|
|
}
|
|
|
|
if ((val & 0x3c) != 0x3c) {
|
|
if (lower > 0 && upper < 0)
|
|
upper = i;
|
|
}
|
|
|
|
pr_debug("0x%02x: compare: 0x%08x ", i, readl(P0_IPS + MPSWDAR));
|
|
for (j = 0; j < 8; j++) {
|
|
pr_debug("0x%08x ", readl(P0_IPS + 0x898 + j * 4));
|
|
}
|
|
pr_debug("\n");
|
|
#endif
|
|
}
|
|
|
|
static void mmdc_sw_read_calib(int ch, u32 wr_value)
|
|
{
|
|
int rd = 1;
|
|
void __iomem *base;
|
|
int i;
|
|
int lower = 0x0, upper = 0x7f;
|
|
|
|
if (ch)
|
|
base = (void *)P1_IPS;
|
|
else
|
|
base = (void *)P0_IPS;
|
|
|
|
/* 1. Precharge */
|
|
mmdc_precharge_all(cs0_enable, cs1_enable);
|
|
|
|
/* 2. Configure pre-defined value */
|
|
writel(wr_value, P0_IPS + MPPDCMPR1);
|
|
|
|
/* 3. Issue write access */
|
|
mmdc_issue_write_access(base);
|
|
|
|
for (i = 0; i < 100; i++) {
|
|
if (mmdc_is_valid(base, 0x40, rd)) {
|
|
goto middle_passed;
|
|
}
|
|
}
|
|
|
|
pr_debug("ch: %d value: 0x%08x middle test failed\n", ch, wr_value);
|
|
return;
|
|
|
|
middle_passed:
|
|
for (i = 0x40; i < 0x7f; i++) {
|
|
if (!mmdc_is_valid(base, i, rd)) {
|
|
upper = i;
|
|
break;
|
|
}
|
|
}
|
|
|
|
for (i = 0; i < 100; i++) {
|
|
if (mmdc_is_valid(base, 0x40, rd)) {
|
|
goto go_on;
|
|
}
|
|
}
|
|
|
|
pr_debug("ch: %d value: 0x%08x middle test 1 failed\n", ch, wr_value);
|
|
return;
|
|
|
|
go_on:
|
|
for (i = 0x40; i >= 0; i--) {
|
|
if (!mmdc_is_valid(base, i, rd)) {
|
|
lower = i;
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (lower > total_lower[ch])
|
|
total_lower[ch] = lower;
|
|
|
|
if (upper < total_upper[ch])
|
|
total_upper[ch] = upper;
|
|
|
|
pr_debug("ch: %d value: 0x%08x lower: %-3d upper: %-3d\n", ch, wr_value, lower, upper);
|
|
}
|
|
|
|
static void mmdc_sw_write_calib(int ch, u32 wr_value)
|
|
{
|
|
int rd = 0;
|
|
void __iomem *base;
|
|
int i;
|
|
int lower = 0x0, upper = 0x7f;
|
|
|
|
if (ch)
|
|
base = (void *)P1_IPS;
|
|
else
|
|
base = (void *)P0_IPS;
|
|
|
|
/* 1. Precharge */
|
|
mmdc_precharge_all(cs0_enable, cs1_enable);
|
|
|
|
/* 2. Configure pre-defined value */
|
|
writel(wr_value, P0_IPS + MPPDCMPR1);
|
|
|
|
/* 3. Issue write access */
|
|
mmdc_issue_write_access(base);
|
|
|
|
for (i = 0; i < 100; i++) {
|
|
if (mmdc_is_valid(base, 0x40, rd)) {
|
|
goto middle_passed;
|
|
}
|
|
}
|
|
|
|
pr_debug("ch: %d value: 0x%08x middle test failed\n", ch, wr_value);
|
|
return;
|
|
|
|
middle_passed:
|
|
for (i = 0x40; i < 0x7f; i++) {
|
|
if (!mmdc_is_valid(base, i, rd)) {
|
|
upper = i;
|
|
break;
|
|
}
|
|
}
|
|
|
|
for (i = 0; i < 100; i++) {
|
|
if (mmdc_is_valid(base, 0x40, rd)) {
|
|
goto go_on;
|
|
}
|
|
}
|
|
|
|
pr_debug("ch: %d value: 0x%08x middle test 1 failed\n", ch, wr_value);
|
|
return;
|
|
|
|
go_on:
|
|
for (i = 0x40; i >= 0; i--) {
|
|
if (!mmdc_is_valid(base, i, rd)) {
|
|
lower = i;
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (lower > total_lower[ch])
|
|
total_lower[ch] = lower;
|
|
|
|
if (upper < total_upper[ch])
|
|
total_upper[ch] = upper;
|
|
|
|
pr_debug("ch: %d value: 0x%08x lower: %-3d upper: %-3d\n", ch, wr_value, lower, upper);
|
|
}
|
|
|
|
int mmdc_do_software_calibration(void)
|
|
{
|
|
u32 s;
|
|
int ch;
|
|
|
|
for (ch = 0; ch < 2; ch++) {
|
|
mmdc_sw_read_calib(ch, 0x00000055);
|
|
mmdc_sw_read_calib(ch, 0x00005500);
|
|
mmdc_sw_read_calib(ch, 0x00550000);
|
|
mmdc_sw_read_calib(ch, 0x55000000);
|
|
mmdc_sw_read_calib(ch, 0x00ffff00);
|
|
mmdc_sw_read_calib(ch, 0xff0000ff);
|
|
mmdc_sw_read_calib(ch, 0x55aaaa55);
|
|
mmdc_sw_read_calib(ch, 0xaa5555aa);
|
|
|
|
for (s = 1; s; s <<= 1)
|
|
mmdc_sw_read_calib(ch, s);
|
|
}
|
|
|
|
printk("ch0 total lower: %d upper: %d avg: 0x%02x\n",
|
|
total_lower[0], total_upper[0],
|
|
(total_lower[0] + total_upper[0]) / 2);
|
|
printk("ch1 total lower: %d upper: %d avg: 0x%02x\n",
|
|
total_lower[1], total_upper[1],
|
|
(total_lower[1] + total_upper[1]) / 2);
|
|
|
|
mmdc_set_dqs(0x40);
|
|
|
|
total_lower[0] = 0;
|
|
total_lower[1] = 0;
|
|
total_upper[0] = 0xff;
|
|
total_upper[1] = 0xff;
|
|
|
|
for (ch = 0; ch < 2; ch++) {
|
|
mmdc_sw_write_calib(ch, 0x00000055);
|
|
mmdc_sw_write_calib(ch, 0x00005500);
|
|
mmdc_sw_write_calib(ch, 0x00550000);
|
|
mmdc_sw_write_calib(ch, 0x55000000);
|
|
mmdc_sw_write_calib(ch, 0x00ffff00);
|
|
mmdc_sw_write_calib(ch, 0xff0000ff);
|
|
mmdc_sw_write_calib(ch, 0x55aaaa55);
|
|
mmdc_sw_write_calib(ch, 0xaa5555aa);
|
|
|
|
for (s = 1; s; s <<= 1)
|
|
mmdc_sw_write_calib(ch, s);
|
|
}
|
|
|
|
printk("ch0 total lower: %d upper: %d avg: 0x%02x\n",
|
|
total_lower[0], total_upper[0],
|
|
(total_lower[0] + total_upper[0]) / 2);
|
|
printk("ch1 total lower: %d upper: %d avg: 0x%02x\n",
|
|
total_lower[1], total_upper[1],
|
|
(total_lower[1] + total_upper[1]) / 2);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#endif /* MMDC_SOFTWARE_CALIBRATION */
|