158 lines
4.0 KiB
C
158 lines
4.0 KiB
C
/*
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* Copyright (C) 2012 Sascha Hauer, Pengutronix
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <common.h>
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#include <init.h>
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#include <environment.h>
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#include <mach/imx6-regs.h>
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#include <fec.h>
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#include <mach/gpio.h>
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#include <asm/armlinux.h>
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#include <generated/mach-types.h>
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#include <partition.h>
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#include <linux/phy.h>
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#include <asm/io.h>
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#include <asm/mmu.h>
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#include <mach/generic.h>
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#include <sizes.h>
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#include <mach/imx6.h>
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#include <mach/devices-imx6.h>
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#include <mach/iomux-mx6.h>
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static iomux_v3_cfg_t arm2_pads[] = {
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/* UART1 */
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MX6Q_PAD_KEY_COL0__UART4_TXD,
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MX6Q_PAD_KEY_ROW0__UART4_RXD,
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MX6Q_PAD_SD1_CLK__USDHC1_CLK,
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MX6Q_PAD_SD1_CMD__USDHC1_CMD,
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MX6Q_PAD_SD1_DAT0__USDHC1_DAT0,
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MX6Q_PAD_SD1_DAT1__USDHC1_DAT1,
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MX6Q_PAD_SD1_DAT2__USDHC1_DAT2,
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MX6Q_PAD_SD1_DAT3__USDHC1_DAT3,
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MX6Q_PAD_SD2_CLK__USDHC2_CLK,
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MX6Q_PAD_SD2_CMD__USDHC2_CMD,
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MX6Q_PAD_SD2_DAT0__USDHC2_DAT0,
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MX6Q_PAD_SD2_DAT1__USDHC2_DAT1,
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MX6Q_PAD_SD2_DAT2__USDHC2_DAT2,
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MX6Q_PAD_SD2_DAT3__USDHC2_DAT3,
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MX6Q_PAD_SD3_CLK__USDHC3_CLK,
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MX6Q_PAD_SD3_CMD__USDHC3_CMD,
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MX6Q_PAD_SD3_DAT0__USDHC3_DAT0,
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MX6Q_PAD_SD3_DAT1__USDHC3_DAT1,
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MX6Q_PAD_SD3_DAT2__USDHC3_DAT2,
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MX6Q_PAD_SD3_DAT3__USDHC3_DAT3,
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MX6Q_PAD_SD3_DAT4__USDHC3_DAT4,
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MX6Q_PAD_SD3_DAT5__USDHC3_DAT5,
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MX6Q_PAD_SD3_DAT6__USDHC3_DAT6,
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MX6Q_PAD_SD3_DAT7__USDHC3_DAT7,
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MX6Q_PAD_GPIO_18__USDHC3_VSELECT,
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MX6Q_PAD_SD4_CLK__USDHC4_CLK,
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MX6Q_PAD_SD4_CMD__USDHC4_CMD,
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MX6Q_PAD_SD4_DAT0__USDHC4_DAT0,
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MX6Q_PAD_SD4_DAT1__USDHC4_DAT1,
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MX6Q_PAD_SD4_DAT2__USDHC4_DAT2,
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MX6Q_PAD_SD4_DAT3__USDHC4_DAT3,
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MX6Q_PAD_SD4_DAT4__USDHC4_DAT4,
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MX6Q_PAD_SD4_DAT5__USDHC4_DAT5,
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MX6Q_PAD_SD4_DAT6__USDHC4_DAT6,
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MX6Q_PAD_SD4_DAT7__USDHC4_DAT7,
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MX6Q_PAD_KEY_COL1__ENET_MDIO,
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MX6Q_PAD_KEY_COL2__ENET_MDC,
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MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC,
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MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0,
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MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1,
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MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2,
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MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3,
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MX6Q_PAD_RGMII_TX_CTL__ENET_RGMII_TX_CTL,
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MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK,
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MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC,
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MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0,
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MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1,
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MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2,
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MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3,
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MX6Q_PAD_RGMII_RX_CTL__ENET_RGMII_RX_CTL,
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MX6Q_PAD_GPIO_0__CCM_CLKO,
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MX6Q_PAD_GPIO_3__CCM_CLKO2,
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};
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static int arm2_mem_init(void)
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{
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arm_add_mem_device("ram0", 0x10000000, SZ_2G);
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return 0;
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}
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mem_initcall(arm2_mem_init);
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static void mx6_rgmii_rework(struct phy_device *dev)
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{
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u16 val;
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/* To enable AR8031 ouput a 125MHz clk from CLK_25M */
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phy_write(dev, 0xd, 0x7);
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phy_write(dev, 0xe, 0x8016);
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phy_write(dev, 0xd, 0x4007);
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val = phy_read(dev, 0xe);
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val &= 0xffe3;
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val |= 0x18;
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phy_write(dev, 0xe, val);
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/* introduce tx clock delay */
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phy_write(dev, 0x1d, 0x5);
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val = phy_read(dev, 0x1e);
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val |= 0x0100;
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phy_write(dev, 0x1e, val);
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}
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static struct fec_platform_data fec_info = {
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.xcv_type = PHY_INTERFACE_MODE_RGMII,
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.phy_init = mx6_rgmii_rework,
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.phy_addr = 0,
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};
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static int arm2_devices_init(void)
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{
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imx6_add_mmc3(NULL);
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imx6_add_fec(&fec_info);
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armlinux_set_bootparams((void *)0x10000100);
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armlinux_set_architecture(3837);
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devfs_add_partition("disk0", 0, SZ_1M, DEVFS_PARTITION_FIXED, "self0");
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devfs_add_partition("disk0", SZ_1M + SZ_1M, SZ_512K, DEVFS_PARTITION_FIXED, "env0");
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return 0;
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}
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device_initcall(arm2_devices_init);
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static int arm2_console_init(void)
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{
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mxc_iomux_v3_setup_multiple_pads(arm2_pads, ARRAY_SIZE(arm2_pads));
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imx6_init_lowlevel();
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imx6_add_uart3();
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return 0;
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}
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console_initcall(arm2_console_init);
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