52 lines
1.1 KiB
ArmAsm
52 lines
1.1 KiB
ArmAsm
#include <config.h>
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#include <mach/imx27-regs.h>
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#include <mach/imx-pll.h>
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#include <linux/linkage.h>
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#define writel(val, reg) \
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ldr r0, =reg; \
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ldr r1, =val; \
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str r1, [r0];
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#define CSCR_VAL MX27_CSCR_USB_DIV(3) | \
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MX27_CSCR_SD_CNT(3) | \
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MX27_CSCR_MSHC_SEL | \
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MX27_CSCR_H264_SEL | \
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MX27_CSCR_SSI1_SEL | \
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MX27_CSCR_SSI2_SEL | \
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MX27_CSCR_MCU_SEL | \
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MX27_CSCR_ARM_SRC_MPLL | \
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MX27_CSCR_SP_SEL | \
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MX27_CSCR_ARM_DIV(0) | \
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MX27_CSCR_FPM_EN | \
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MX27_CSCR_SPEN | \
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MX27_CSCR_MPEN | \
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MX27_CSCR_AHB_DIV(1)
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ENTRY(neso_pll_init)
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/* 399 MHz */
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writel(IMX_PLL_PD(0) |
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IMX_PLL_MFD(51) |
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IMX_PLL_MFI(7) |
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IMX_PLL_MFN(35), MX27_CCM_BASE_ADDR + MX27_MPCTL0)
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/* SPLL = 2 * 26 * 4.61538 MHz = 240 MHz */
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writel(IMX_PLL_PD(1) |
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IMX_PLL_MFD(12) |
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IMX_PLL_MFI(9) |
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IMX_PLL_MFN(3), MX27_CCM_BASE_ADDR + MX27_SPCTL0)
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writel(CSCR_VAL | MX27_CSCR_MPLL_RESTART | MX27_CSCR_SPLL_RESTART,
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MX27_CCM_BASE_ADDR + MX27_CSCR)
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ldr r2, =16000
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1:
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subs r2, r2, #1
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nop
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bcs 1b
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mov pc, lr
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ENDPROC(neso_pll_init)
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