a8d19f1f2f
All the smcs family chips 91c94, 91c96, 91c100, 91c111 share almost the same behavior and register sets. The noticeable exceptions are coped with in this patch, ie : - 91c94 and 91c96 only have an internal 10 Mbps phy The registers used for phy discovery on later chips will corrupt the 91c96 state. - 91c94 and 91c96 have a control and config register quite different from their 91c1xx conterparts A platform data user defined couple of registers is introduced. If these values are 0, 91c1xx legacy behavior is assumed. Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> |
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| .. | ||
| davinci_emac.h | ||
| designware.h | ||
| smc91111.h | ||