For all users fix or add the error check. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
111 lines
2.5 KiB
C
111 lines
2.5 KiB
C
/*
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* Copyright (C) 2013 Lucas Stach <l.stach@pengutronix.de>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**
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* @file
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* @brief Device driver for the Tegra 20 timer, which exposes a clocksource.
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*/
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#include <common.h>
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#include <clock.h>
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#include <init.h>
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#include <io.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <mach/lowlevel.h>
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/* register definitions */
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#define TIMERUS_CNTR_1US 0x10
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#define TIMERUS_USEC_CFG 0x14
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static void __iomem *timer_base;
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static uint64_t tegra20_timer_cs_read(void)
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{
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return readl(timer_base + TIMERUS_CNTR_1US);
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}
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static struct clocksource cs = {
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.read = tegra20_timer_cs_read,
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.mask = CLOCKSOURCE_MASK(32),
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};
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static int tegra20_timer_probe(struct device_d *dev)
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{
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u32 reg;
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/* use only one timer */
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if (timer_base)
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return -EBUSY;
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timer_base = dev_request_mem_region(dev, 0);
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if (IS_ERR(timer_base)) {
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dev_err(dev, "could not get memory region\n");
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return PTR_ERR(timer_base);
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}
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/*
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* calibrate timer to run at 1MHz
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* TIMERUS_USEC_CFG selects the scale down factor with bits [0:7]
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* representing the divisor and bits [8:15] representing the dividend
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* each in n+1 form.
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*/
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switch (tegra_get_osc_clock()) {
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case 12000000:
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reg = 0x000b;
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break;
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case 13000000:
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reg = 0x000c;
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break;
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case 19200000:
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reg = 0x045f;
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break;
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case 26000000:
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reg = 0x0019;
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break;
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default:
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reg = 0;
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dev_warn(dev, "unknown timer clock rate\n");
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break;
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}
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writel(reg, timer_base + TIMERUS_USEC_CFG);
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cs.mult = clocksource_hz2mult(1000000, cs.shift);
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init_clock(&cs);
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return 0;
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}
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static __maybe_unused struct of_device_id tegra20_timer_dt_ids[] = {
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{
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.compatible = "nvidia,tegra20-timer",
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}, {
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/* sentinel */
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}
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};
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static struct driver_d tegra20_timer_driver = {
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.probe = tegra20_timer_probe,
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.name = "tegra20-timer",
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.of_compatible = DRV_OF_COMPAT(tegra20_timer_dt_ids),
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};
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static int tegra20_timer_init(void)
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{
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return platform_driver_register(&tegra20_timer_driver);
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}
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core_initcall(tegra20_timer_init);
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