this implementation is based on linux one (v2.6.35-rc5-76-gd0c6f62) it will calculate all the clock dynamically instead of statictly this will use also the new clock framework it will also print the clock status after the console init Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
259 lines
6.2 KiB
C
259 lines
6.2 KiB
C
/*
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*
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* (c) 2008 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <linux/clk.h>
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#include <errno.h>
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#include <asm/io.h>
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#include <mach/gpio.h>
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#include <gpio.h>
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static int gpio_banks;
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static struct at91_gpio_bank *gpio;
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static inline void __iomem *pin_to_controller(unsigned pin)
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{
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pin -= PIN_BASE;
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pin /= 32;
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if (likely(pin < gpio_banks))
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return gpio[pin].regbase;
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return NULL;
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}
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static inline unsigned pin_to_mask(unsigned pin)
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{
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pin -= PIN_BASE;
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return 1 << (pin % 32);
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}
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/*
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* mux the pin to the "GPIO" peripheral role.
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*/
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int at91_set_GPIO_periph(unsigned pin, int use_pullup)
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{
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void __iomem *pio = pin_to_controller(pin);
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unsigned mask = pin_to_mask(pin);
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if (!pio)
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return -EINVAL;
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__raw_writel(mask, pio + PIO_IDR);
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__raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
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__raw_writel(mask, pio + PIO_PER);
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return 0;
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}
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EXPORT_SYMBOL(at91_set_GPIO_periph);
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/*
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* mux the pin to the "A" internal peripheral role.
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*/
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int at91_set_A_periph(unsigned pin, int use_pullup)
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{
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void __iomem *pio = pin_to_controller(pin);
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unsigned mask = pin_to_mask(pin);
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if (!pio)
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return -EINVAL;
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__raw_writel(mask, pio + PIO_IDR);
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__raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
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__raw_writel(mask, pio + PIO_ASR);
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__raw_writel(mask, pio + PIO_PDR);
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return 0;
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}
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EXPORT_SYMBOL(at91_set_A_periph);
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/*
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* mux the pin to the "B" internal peripheral role.
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*/
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int at91_set_B_periph(unsigned pin, int use_pullup)
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{
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void __iomem *pio = pin_to_controller(pin);
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unsigned mask = pin_to_mask(pin);
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if (!pio)
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return -EINVAL;
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__raw_writel(mask, pio + PIO_IDR);
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__raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
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__raw_writel(mask, pio + PIO_BSR);
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__raw_writel(mask, pio + PIO_PDR);
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return 0;
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}
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EXPORT_SYMBOL(at91_set_B_periph);
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/*
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* mux the pin to the gpio controller (instead of "A" or "B" peripheral), and
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* configure it for an input.
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*/
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int at91_set_gpio_input(unsigned pin, int use_pullup)
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{
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void __iomem *pio = pin_to_controller(pin);
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unsigned mask = pin_to_mask(pin);
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if (!pio)
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return -EINVAL;
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__raw_writel(mask, pio + PIO_IDR);
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__raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
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__raw_writel(mask, pio + PIO_ODR);
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__raw_writel(mask, pio + PIO_PER);
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return 0;
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}
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EXPORT_SYMBOL(at91_set_gpio_input);
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/*
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* mux the pin to the gpio controller (instead of "A" or "B" peripheral),
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* and configure it for an output.
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*/
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int at91_set_gpio_output(unsigned pin, int value)
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{
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void __iomem *pio = pin_to_controller(pin);
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unsigned mask = pin_to_mask(pin);
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if (!pio)
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return -EINVAL;
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__raw_writel(mask, pio + PIO_IDR);
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__raw_writel(mask, pio + PIO_PUDR);
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__raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
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__raw_writel(mask, pio + PIO_OER);
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__raw_writel(mask, pio + PIO_PER);
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return 0;
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}
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EXPORT_SYMBOL(at91_set_gpio_output);
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/*
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* enable/disable the glitch filter; mostly used with IRQ handling.
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*/
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int at91_set_deglitch(unsigned pin, int is_on)
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{
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void __iomem *pio = pin_to_controller(pin);
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unsigned mask = pin_to_mask(pin);
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if (!pio)
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return -EINVAL;
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__raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR));
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return 0;
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}
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EXPORT_SYMBOL(at91_set_deglitch);
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/*
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* enable/disable the multi-driver; This is only valid for output and
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* allows the output pin to run as an open collector output.
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*/
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int at91_set_multi_drive(unsigned pin, int is_on)
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{
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void __iomem *pio = pin_to_controller(pin);
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unsigned mask = pin_to_mask(pin);
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if (!pio)
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return -EINVAL;
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__raw_writel(mask, pio + (is_on ? PIO_MDER : PIO_MDDR));
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return 0;
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}
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EXPORT_SYMBOL(at91_set_multi_drive);
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/*
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* assuming the pin is muxed as a gpio output, set its value.
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*/
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int at91_set_gpio_value(unsigned pin, int value)
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{
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void __iomem *pio = pin_to_controller(pin);
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unsigned mask = pin_to_mask(pin);
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if (!pio)
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return -EINVAL;
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__raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
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return 0;
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}
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EXPORT_SYMBOL(at91_set_gpio_value);
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/*
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* read the pin's value (works even if it's not muxed as a gpio).
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*/
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int at91_get_gpio_value(unsigned pin)
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{
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void __iomem *pio = pin_to_controller(pin);
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unsigned mask = pin_to_mask(pin);
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u32 pdsr;
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if (!pio)
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return -EINVAL;
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pdsr = __raw_readl(pio + PIO_PDSR);
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return (pdsr & mask) != 0;
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}
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EXPORT_SYMBOL(at91_get_gpio_value);
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int gpio_direction_input(unsigned pin)
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{
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void __iomem *pio = pin_to_controller(pin);
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unsigned mask = pin_to_mask(pin);
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if (!pio || !(__raw_readl(pio + PIO_PSR) & mask))
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return -EINVAL;
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__raw_writel(mask, pio + PIO_ODR);
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return 0;
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}
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EXPORT_SYMBOL(gpio_direction_input);
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int gpio_direction_output(unsigned pin, int value)
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{
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void __iomem *pio = pin_to_controller(pin);
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unsigned mask = pin_to_mask(pin);
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if (!pio || !(__raw_readl(pio + PIO_PSR) & mask))
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return -EINVAL;
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__raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
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__raw_writel(mask, pio + PIO_OER);
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return 0;
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}
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EXPORT_SYMBOL(gpio_direction_output);
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/*--------------------------------------------------------------------------*/
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int at91_gpio_init(struct at91_gpio_bank *data, int nr_banks)
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{
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unsigned i;
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struct at91_gpio_bank *last;
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gpio = data;
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gpio_banks = nr_banks;
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for (i = 0, last = NULL; i < nr_banks; i++, last = data, data++) {
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data->chipbase = PIN_BASE + i * 32;
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data->regbase = data->offset +
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(void __iomem *)AT91_BASE_SYS;
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/* enable PIO controller's clock */
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clk_enable(data->clock);
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/* AT91SAM9263_ID_PIOCDE groups PIOC, PIOD, PIOE */
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if (last && last->id == data->id)
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last->next = data;
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}
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return 0;
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}
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