393 lines
11 KiB
C
393 lines
11 KiB
C
/*
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* (C) Copyright 2010 Juergen Beisert - Pengutronix <kernel@pengutronix.de>
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*
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* This code is based partially on code that has:
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*
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* (c) 2008 Embedded Alley Solutions, Inc.
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* (C) Copyright 2009-2010 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <common.h>
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#include <init.h>
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#include <io.h>
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#include <mach/imx-regs.h>
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#include <mach/generic.h>
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#include <mach/clock.h>
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#define HW_CLKCTRL_PLL0CTRL0 0x000
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#define HW_CLKCTRL_PLL0CTRL1 0x010
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#define HW_CLKCTRL_PLL1CTRL0 0x020
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#define HW_CLKCTRL_PLL1CTRL1 0x030
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#define HW_CLKCTRL_PLL2CTRL0 0x040
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# define CLKCTRL_PLL2CTRL0_CLKGATE (1 << 31)
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# define CLKCTRL_PLL2CTRL0_POWER (1 << 23)
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#define HW_CLKCTRL_CPU 0x50
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# define GET_CPU_XTAL_DIV(x) (((x) >> 16) & 0x3ff)
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# define GET_CPU_PLL_DIV(x) ((x) & 0x3f)
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#define HW_CLKCTRL_HBUS 0x60
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#define HW_CLKCTRL_XBUS 0x70
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#define HW_CLKCTRL_XTAL 0x080
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#define HW_CLKCTRL_SSP0 0x090
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#define HW_CLKCTRL_SSP1 0x0a0
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#define HW_CLKCTRL_SSP2 0x0b0
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#define HW_CLKCTRL_SSP3 0x0c0
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/* note: no set/clear register! */
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# define CLKCTRL_SSP_CLKGATE (1 << 31)
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# define CLKCTRL_SSP_BUSY (1 << 29)
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# define CLKCTRL_SSP_DIV_FRAC_EN (1 << 9)
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# define CLKCTRL_SSP_DIV_MASK 0x1ff
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# define GET_SSP_DIV(x) ((x) & CLKCTRL_SSP_DIV_MASK)
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# define SET_SSP_DIV(x) ((x) & CLKCTRL_SSP_DIV_MASK)
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#define HW_CLKCTRL_GPMI 0x0d0
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/* note: no set/clear register! */
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#define HW_CLKCTRL_SPDIF 0x0e0
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/* note: no set/clear register! */
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#define HW_CLKCTRL_EMI 0xf0
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/* note: no set/clear register! */
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# define CLKCTRL_EMI_CLKGATE (1 << 31)
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# define GET_EMI_XTAL_DIV(x) (((x) >> 8) & 0xf)
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# define GET_EMI_PLL_DIV(x) ((x) & 0x3f)
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#define HW_CLKCTRL_SAIF0 0x100
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#define HW_CLKCTRL_SAIF1 0x110
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#define HW_CLKCTRL_DIS_LCDIF 0x120
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# define CLKCTRL_DIS_LCDIF_GATE (1 << 31)
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# define CLKCTRL_DIS_LCDIF_BUSY (1 << 29)
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# define SET_DIS_LCDIF_DIV(x) ((x) & 0x1fff)
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# define GET_DIS_LCDIF_DIV(x) ((x) & 0x1fff)
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#define HW_CLKCTRL_ETM 0x130
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#define HW_CLKCTRL_ENET 0x140
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# define SET_CLKCTRL_ENET_DIV(x) (((x) & 0x3f) << 21)
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# define SET_CLKCTRL_ENET_SEL(x) (((x) & 0x3) << 19)
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# define CLKCTRL_ENET_CLK_OUT_EN (1 << 18)
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#define HW_CLKCTRL_HSADC 0x150
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#define HW_CLKCTRL_FLEXCAN 0x160
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#define HW_CLKCTRL_FRAC0 0x1b0
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# define CLKCTRL_FRAC_CLKGATEIO0 (1 << 31)
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# define GET_IO0FRAC(x) (((x) >> 24) & 0x3f)
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# define SET_IO0FRAC(x) (((x) & 0x3f) << 24)
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# define CLKCTRL_FRAC_CLKGATEIO1 (1 << 23)
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# define GET_IO1FRAC(x) (((x) >> 16) & 0x3f)
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# define SET_IO1FRAC(x) (((x) & 0x3f) << 16)
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# define CLKCTRL_FRAC_CLKGATEEMI (1 << 15)
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# define GET_EMIFRAC(x) (((x) >> 8) & 0x3f)
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# define CLKCTRL_FRAC_CLKGATECPU (1 << 7)
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# define GET_CPUFRAC(x) ((x) & 0x3f)
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#define HW_CLKCTRL_FRAC1 0x1c0
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# define CLKCTRL_FRAC_CLKGATEGPMI (1 << 23)
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# define GET_GPMIFRAC(x) (((x) >> 16) & 0x3f)
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# define CLKCTRL_FRAC_CLKGATEHSADC (1 << 15)
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# define GET_HSADCFRAC(x) (((x) >> 8) & 0x3f)
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# define CLKCTRL_FRAC_CLKGATEPIX (1 << 7)
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# define GET_PIXFRAC(x) ((x) & 0x3f)
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# define SET_PIXFRAC(x) ((x) & 0x3f)
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#define HW_CLKCTRL_CLKSEQ 0x1d0
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# define CLKCTRL_CLKSEQ_BYPASS_CPU (1 << 18)
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# define CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF (1 << 14)
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# define CLKCTRL_CLKSEQ_BYPASS_ETM (1 << 8)
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# define CLKCTRL_CLKSEQ_BYPASS_EMI (1 << 7)
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# define CLKCTRL_CLKSEQ_BYPASS_SSP3 (1 << 6)
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# define CLKCTRL_CLKSEQ_BYPASS_SSP2 (1 << 5)
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# define CLKCTRL_CLKSEQ_BYPASS_SSP1 (1 << 4)
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# define CLKCTRL_CLKSEQ_BYPASS_SSP0 (1 << 3)
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# define CLKCTRL_CLKSEQ_BYPASS_GPMI (1 << 2)
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# define CLKCTRL_CLKSEQ_BYPASS_SAIF1 (1 << 1)
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# define CLKCTRL_CLKSEQ_BYPASS_SAIF0 (1 << 0)
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#define HW_CLKCTRL_RESET 0x1e0
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#define HW_CLKCTRL_STATUS 0x1f0
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#define HW_CLKCTRL_VERSION 0x200
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unsigned imx_get_mpllclk(void)
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{
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/* the main PLL runs at 480 MHz */
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return 480000000;
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}
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unsigned imx_get_xtalclk(void)
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{
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/* the external reference runs at 24 MHz */
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return 24000000;
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}
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unsigned imx_get_fecclk(void)
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{
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/* this PLL always runs at 50 MHz */
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return 50000000;
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}
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/* used for the SDRAM controller */
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unsigned imx_get_emiclk(void)
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{
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uint32_t reg;
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unsigned rate;
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if (readl(IMX_CCM_BASE + HW_CLKCTRL_EMI) & CLKCTRL_EMI_CLKGATE)
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return 0; /* clock is off */
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if (readl(IMX_CCM_BASE + HW_CLKCTRL_CLKSEQ) & CLKCTRL_CLKSEQ_BYPASS_EMI)
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return imx_get_xtalclk() /
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GET_EMI_XTAL_DIV(readl(IMX_CCM_BASE + HW_CLKCTRL_EMI));
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rate = imx_get_mpllclk() / 1000;
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reg = readl(IMX_CCM_BASE + HW_CLKCTRL_FRAC0);
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if (!(reg & CLKCTRL_FRAC_CLKGATEEMI)) {
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rate *= 18;
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rate /= GET_EMIFRAC(reg);
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}
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return (rate / GET_EMI_PLL_DIV(readl(IMX_CCM_BASE + HW_CLKCTRL_EMI)))
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* 1000;
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}
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/*
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* Source of ssp, gpmi, ir
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* @param index 0 or 1 for ioclk0 or ioclock1
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*/
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unsigned imx_get_ioclk(unsigned index)
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{
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uint32_t reg;
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unsigned rate = imx_get_mpllclk() / 1000;
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reg = readl(IMX_CCM_BASE + HW_CLKCTRL_FRAC0);
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switch (index) {
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case 0:
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if (reg & CLKCTRL_FRAC_CLKGATEIO0)
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return 0; /* clock is off */
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rate *= 18;
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rate /= GET_IO0FRAC(reg);
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break;
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case 1:
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if (reg & CLKCTRL_FRAC_CLKGATEIO1)
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return 0; /* clock is off */
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rate *= 18;
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rate /= GET_IO1FRAC(reg);
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break;
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}
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return rate * 1000;
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}
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/**
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* Setup a new frequency to the IOCLK domain.
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* @param index 0 or 1 for ioclk0 or ioclock1
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* @param nc New frequency in [Hz]
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*
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* The FRAC divider for the IOCLK must be between 18 (* 18/18) and 35 (* 18/35)
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*
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* ioclock0 is the shared clock source of SSP0/SSP1, ioclock1 the shared clock
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* source of SSP2/SSP3
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*/
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unsigned imx_set_ioclk(unsigned index, unsigned nc)
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{
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uint32_t reg;
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unsigned div;
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nc /= 1000;
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div = (imx_get_mpllclk() / 1000) * 18;
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div = DIV_ROUND_CLOSEST(div, nc);
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if (div > 0x3f)
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div = 0x3f;
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switch (index) {
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case 0:
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reg = readl(IMX_CCM_BASE + HW_CLKCTRL_FRAC0) &
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~(SET_IO0FRAC(0x3f));
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/* mask the current settings */
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writel(reg | SET_IO0FRAC(div), IMX_CCM_BASE + HW_CLKCTRL_FRAC0);
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/* enable the IO clock at its new frequency */
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writel(CLKCTRL_FRAC_CLKGATEIO0,
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IMX_CCM_BASE + HW_CLKCTRL_FRAC0 + BIT_CLR);
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break;
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case 1:
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reg = readl(IMX_CCM_BASE + HW_CLKCTRL_FRAC0) &
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~(SET_IO1FRAC(0x3f));
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/* mask the current settings */
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writel(reg | SET_IO1FRAC(div), IMX_CCM_BASE + HW_CLKCTRL_FRAC0);
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/* enable the IO clock at its new frequency */
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writel(CLKCTRL_FRAC_CLKGATEIO1,
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IMX_CCM_BASE + HW_CLKCTRL_FRAC0 + BIT_CLR);
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break;
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}
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return imx_get_ioclk(index);
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}
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/* this is CPU core clock */
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unsigned imx_get_armclk(void)
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{
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uint32_t reg;
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unsigned rate;
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if (readl(IMX_CCM_BASE + HW_CLKCTRL_CLKSEQ) & CLKCTRL_CLKSEQ_BYPASS_CPU)
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return imx_get_xtalclk() /
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GET_CPU_XTAL_DIV(readl(IMX_CCM_BASE + HW_CLKCTRL_CPU));
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reg = readl(IMX_CCM_BASE + HW_CLKCTRL_FRAC0);
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if (reg & CLKCTRL_FRAC_CLKGATECPU)
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return 0; /* should not possible, shouldn't it? */
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rate = (imx_get_mpllclk() / 1000) * 18;
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rate /= GET_CPUFRAC(reg);
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return (rate / GET_CPU_PLL_DIV(readl(IMX_CCM_BASE + HW_CLKCTRL_CPU)))
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* 1000;
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}
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/* this is the AHB and APBH bus clock */
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unsigned imx_get_hclk(void)
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{
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unsigned rate = imx_get_armclk() / 1000;
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if (readl(IMX_CCM_BASE + HW_CLKCTRL_HBUS) & 0x20) {
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rate *= readl(IMX_CCM_BASE + HW_CLKCTRL_HBUS) & 0x1f;
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rate /= 32;
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} else
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rate /= readl(IMX_CCM_BASE + HW_CLKCTRL_HBUS) & 0x1f;
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return rate * 1000;
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}
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/*
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* Source of UART, debug UART, audio, PWM, dri, timer, digctl
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*/
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unsigned imx_get_xclk(void)
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{
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/* runs from the 24 MHz crystal reference */
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unsigned rate = imx_get_xtalclk();
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return rate / (readl(IMX_CCM_BASE + HW_CLKCTRL_XBUS) & 0x3ff);
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}
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/**
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* @param index The SSP unit (0...3)
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*/
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unsigned imx_get_sspclk(unsigned index)
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{
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unsigned rate, offset, shift, ioclk_index;
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if (index > 3) {
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pr_debug("Unknown SSP unit: %u\n", index);
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return 0;
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}
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ioclk_index = index >> 1;
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offset = HW_CLKCTRL_SSP0 + (0x10 * index);
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shift = CLKCTRL_CLKSEQ_BYPASS_SSP0 << index;
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if (readl(IMX_CCM_BASE + offset) & CLKCTRL_SSP_CLKGATE)
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return 0; /* clock is off */
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if (readl(IMX_CCM_BASE + HW_CLKCTRL_CLKSEQ) & shift)
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rate = imx_get_xtalclk();
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else
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rate = imx_get_ioclk(ioclk_index);
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return rate / GET_SSP_DIV(readl(IMX_CCM_BASE + offset));
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}
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/**
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* @param index The SSP unit (0...3)
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* @param nc New frequency in [Hz]
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* @param high != 0 if ioclk should be the source
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* @return The new possible frequency
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*/
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unsigned imx_set_sspclk(unsigned index, unsigned nc, int high)
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{
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uint32_t reg;
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unsigned ssp_div, offset, shift, ioclk_index;
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if (index > 3) {
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pr_debug("Unknown SSP unit: %u\n", index);
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return 0;
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}
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ioclk_index = index >> 1;
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offset = HW_CLKCTRL_SSP0 + (0x10 * index);
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shift = CLKCTRL_CLKSEQ_BYPASS_SSP0 << index;
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reg = readl(IMX_CCM_BASE + offset) & ~CLKCTRL_SSP_CLKGATE;
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/* Datasheet says: Do not change the DIV setting if the clock is off */
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writel(reg, IMX_CCM_BASE + offset);
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/* Wait while clock is gated */
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while (readl(IMX_CCM_BASE + offset) & CLKCTRL_SSP_CLKGATE)
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;
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if (high)
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ssp_div = imx_get_ioclk(ioclk_index);
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else
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ssp_div = imx_get_xtalclk();
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if (nc > ssp_div) {
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printf("Cannot setup SSP unit clock to %u kHz, base clock is "
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"only %u kHz\n", nc, ssp_div);
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ssp_div = 1;
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} else {
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ssp_div = DIV_ROUND_UP(ssp_div, nc);
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if (ssp_div > CLKCTRL_SSP_DIV_MASK)
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ssp_div = CLKCTRL_SSP_DIV_MASK;
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}
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/* Set new divider value */
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reg = readl(IMX_CCM_BASE + offset) & ~CLKCTRL_SSP_DIV_MASK;
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writel(reg | SET_SSP_DIV(ssp_div), IMX_CCM_BASE + offset);
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/* Wait until new divider value is set */
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while (readl(IMX_CCM_BASE + offset) & CLKCTRL_SSP_BUSY)
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;
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if (high)
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/* switch to ioclock */
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writel(shift, IMX_CCM_BASE + HW_CLKCTRL_CLKSEQ + BIT_CLR);
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else
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/* switch to 24 MHz crystal */
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writel(shift, IMX_CCM_BASE + HW_CLKCTRL_CLKSEQ + BIT_SET);
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return imx_get_sspclk(index);
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}
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void imx_enable_enetclk(void)
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{
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uint32_t reg;
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/* wake up main enet PLL */
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reg = readl(IMX_CCM_BASE + HW_CLKCTRL_PLL2CTRL0);
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if (!(reg & CLKCTRL_PLL2CTRL0_POWER)) {
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reg |= CLKCTRL_PLL2CTRL0_POWER;
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writel(reg, IMX_CCM_BASE + HW_CLKCTRL_PLL2CTRL0);
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udelay(50); /* wait until this PLL locks */
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}
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reg &= ~CLKCTRL_PLL2CTRL0_CLKGATE;
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writel(reg, IMX_CCM_BASE + HW_CLKCTRL_PLL2CTRL0);
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writel(SET_CLKCTRL_ENET_DIV(1) | SET_CLKCTRL_ENET_SEL(0) |
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CLKCTRL_ENET_CLK_OUT_EN, /* FIXME may be platform specific */
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IMX_CCM_BASE + HW_CLKCTRL_ENET);
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}
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void imx_dump_clocks(void)
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{
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printf("mpll: %10u kHz\n", imx_get_mpllclk() / 1000);
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printf("arm: %10u kHz\n", imx_get_armclk() / 1000);
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printf("ioclk0: %10u kHz\n", imx_get_ioclk(0) / 1000);
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printf("ioclk1: %10u kHz\n", imx_get_ioclk(1) / 1000);
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printf("emiclk: %10u kHz\n", imx_get_emiclk() / 1000);
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printf("hclk: %10u kHz\n", imx_get_hclk() / 1000);
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printf("xclk: %10u kHz\n", imx_get_xclk() / 1000);
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printf("ssp0: %10u kHz\n", imx_get_sspclk(0) / 1000);
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printf("ssp1: %10u kHz\n", imx_get_sspclk(1) / 1000);
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printf("ssp2: %10u kHz\n", imx_get_sspclk(2) / 1000);
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printf("ssp3: %10u kHz\n", imx_get_sspclk(3) / 1000);
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}
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