184 lines
4.3 KiB
C
184 lines
4.3 KiB
C
/*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <mach/imx-regs.h>
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#include <asm/io.h>
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#include <mach/clock.h>
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#include <init.h>
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unsigned long imx_get_mpllclk(void)
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{
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ulong mpctl = readl(IMX_CCM_BASE + CCM_MPCTL);
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return imx_decode_pll(mpctl, CONFIG_MX35_HCLK_FREQ);
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}
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unsigned long imx_get_ppllclk(void)
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{
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ulong ppctl = readl(IMX_CCM_BASE + CCM_PPCTL);
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return imx_decode_pll(ppctl, CONFIG_MX35_HCLK_FREQ);
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}
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struct arm_ahb_div {
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unsigned char arm, ahb, sel;
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};
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static struct arm_ahb_div clk_consumer[] = {
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{ .arm = 1, .ahb = 4, .sel = 0},
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{ .arm = 1, .ahb = 3, .sel = 1},
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{ .arm = 2, .ahb = 2, .sel = 0},
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{ .arm = 0, .ahb = 0, .sel = 0},
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{ .arm = 0, .ahb = 0, .sel = 0},
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{ .arm = 0, .ahb = 0, .sel = 0},
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{ .arm = 4, .ahb = 1, .sel = 0},
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{ .arm = 1, .ahb = 5, .sel = 0},
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{ .arm = 1, .ahb = 8, .sel = 0},
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{ .arm = 1, .ahb = 6, .sel = 1},
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{ .arm = 2, .ahb = 4, .sel = 0},
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{ .arm = 0, .ahb = 0, .sel = 0},
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{ .arm = 0, .ahb = 0, .sel = 0},
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{ .arm = 0, .ahb = 0, .sel = 0},
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{ .arm = 4, .ahb = 2, .sel = 0},
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{ .arm = 0, .ahb = 0, .sel = 0},
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};
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unsigned long imx_get_armclk(void)
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{
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unsigned long pdr0 = readl(IMX_CCM_BASE + CCM_PDR0);
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struct arm_ahb_div *aad;
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unsigned long fref = imx_get_mpllclk();
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/* consumer path is selected */
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aad = &clk_consumer[(pdr0 >> 16) & 0xf];
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if (aad->sel)
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fref = fref * 3 / 4;
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return fref / aad->arm;
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}
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unsigned long imx_get_ahbclk(void)
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{
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unsigned long pdr0 = readl(IMX_CCM_BASE + CCM_PDR0);
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struct arm_ahb_div *aad;
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unsigned long fref = imx_get_armclk();
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aad = &clk_consumer[(pdr0 >> 16) & 0xf];
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return fref / aad->ahb;
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}
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unsigned long imx_get_ipgclk(void)
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{
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ulong clk = imx_get_ahbclk();
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return clk >> 1;
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}
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static unsigned long get_3_3_div(unsigned long in)
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{
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return (((in >> 3) & 0x7) + 1) * ((in & 0x7) + 1);
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}
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unsigned long imx_get_gptclk(void)
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{
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ulong pdr0 = readl(IMX_CCM_BASE + CCM_PDR0);
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ulong pdr4 = readl(IMX_CCM_BASE + CCM_PDR4);
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ulong div;
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ulong fref;
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if (pdr0 & PDR0_PER_SEL) {
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/* perclk from arm high frequency clock and synched with AHB clki */
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fref = imx_get_armclk();
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div = get_3_3_div((pdr4 >> 16));
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} else {
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/* perclk from AHB divided clock */
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fref = imx_get_ahbclk();
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div = ((pdr0 >> 12) & 0x7) + 1; //FIXME check datasheet 111 -> 7 ?
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}
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return fref / div;
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}
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unsigned long imx_get_uartclk(void)
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{
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unsigned long pdr3 = readl(IMX_CCM_BASE + CCM_PDR3);
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unsigned long pdr4 = readl(IMX_CCM_BASE + CCM_PDR4);
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unsigned long div = get_3_3_div(pdr4 >> 10);
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if (pdr3 & (1 << 14))
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return imx_get_armclk() / div;
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else
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return imx_get_ppllclk() / div;
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}
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ulong imx_get_fecclk(void)
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{
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return imx_get_ipgclk();
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}
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void imx_dump_clocks(void)
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{
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printf("mpll: %10d Hz\n", imx_get_mpllclk());
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printf("ppll: %10d Hz\n", imx_get_ppllclk());
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printf("arm: %10d Hz\n", imx_get_armclk());
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printf("gpt: %10d Hz\n", imx_get_gptclk());
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printf("ahb: %10d Hz\n", imx_get_ahbclk());
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printf("ipg: %10d Hz\n", imx_get_ipgclk());
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printf("uart: %10d Hz\n", imx_get_uartclk());
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}
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/*
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* Set the divider of the CLKO pin. Returns
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* the new divider (which may be smaller
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* than the desired one)
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*/
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int imx_clko_set_div(int div)
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{
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unsigned long cosr = readl(IMX_CCM_BASE + CCM_COSR);
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div -= 1;
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div &= 0x3f;
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cosr &= ~(0x3f << 10);
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cosr |= div << 10;
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writel(cosr, IMX_CCM_BASE + CCM_COSR);
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return div + 1;
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}
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/*
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* Set the clock source for the CLKO pin
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*/
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void imx_clko_set_src(int src)
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{
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unsigned long cosr = readl(IMX_CCM_BASE + CCM_COSR);
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if (src < 0) {
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cosr &= ~(1 << 5);
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writel(cosr, IMX_CCM_BASE + CCM_COSR);
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return;
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}
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cosr |= 1 << 5;
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cosr &= ~0x1f;
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cosr &= ~(1 << 6);
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cosr |= src & 0x1f;
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writel(cosr, IMX_CCM_BASE + CCM_COSR);
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}
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