122 lines
3.1 KiB
C
122 lines
3.1 KiB
C
/**
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* @file
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* @brief This file contains exported structure for NAND
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*
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* FileName: include/asm-arm/arch-omap/gpmc_nand.h
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*
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* OMAP's General Purpose Memory Controller (GPMC) has a NAND controller
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* embedded. this file provides the platform data structure required to
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* hook on to it.
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*
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*/
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/*
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* (C) Copyright 2008
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* Texas Instruments, <www.ti.com>
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* Nishanth Menon <x0nishan@ti.com>
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*
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* Originally from Linux kernel:
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* http://linux.omap.com/pub/kernel/3430zoom/linux-ldp-v1.3.tar.gz
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* include/asm-arm/arch-omap/nand.h
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*
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* Copyright (C) 2006 Micron Technology Inc.
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* Author: Shahrom Sharif-Kashani
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_OMAP_NAND_GPMC_H
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#define __ASM_OMAP_NAND_GPMC_H
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/nand.h>
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#include <linux/mtd/nand_ecc.h>
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/** omap nand platform data structure */
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struct gpmc_nand_platform_data {
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/** Chip select you want to use */
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int cs;
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struct mtd_partition *parts;
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int nr_parts;
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/** If there are any special setups you'd want to do */
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int (*nand_setup) (struct gpmc_nand_platform_data *);
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/** set up if we want H/w ECC here and other
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* platform specific configs here
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*/
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unsigned short plat_options;
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/** setup any special options */
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unsigned int options;
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/** set up device access as 8,16 as per GPMC config */
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char device_width;
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/** Set this to WAITx+1, so GPMC WAIT0 will be 1 and so on. */
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char wait_mon_pin;
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/** Set this to the max timeout for the device */
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uint64_t max_timeout;
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/* if you like a custom oob use this. */
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struct nand_ecclayout *oob;
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/** platform specific private data */
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void *priv;
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};
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/** Platform specific options definitions */
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/** plat_options: Wait montioring pin low */
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#define NAND_WAITPOL_LOW (0 << 0)
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/** plat_options: Wait montioring pin high */
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#define NAND_WAITPOL_HIGH (1 << 0)
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#define NAND_WAITPOL_MASK (1 << 0)
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#ifdef CONFIG_NAND_OMAP_GPMC_HWECC
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/** plat_options: hw ecc enabled */
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#define NAND_HWECC_ENABLE (1 << 1)
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#endif
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/** plat_options: hw ecc disabled */
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#define NAND_HWECC_DISABLE (0 << 1)
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#define NAND_HWECC_MASK (1 << 1)
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/* Typical BOOTROM oob layouts-requires hwecc **/
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#ifdef CONFIG_NAND_OMAP_GPMC_HWECC
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/** Large Page x8 NAND device Layout */
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#define GPMC_NAND_ECC_LP_x8_LAYOUT {\
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.eccbytes = 12,\
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.eccpos = {1, 2, 3, 4, 5, 6, 7, 8,\
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9, 10, 11, 12},\
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.oobfree = {\
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{.offset = 60,\
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.length = 2 } } \
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}
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/** Large Page x16 NAND device Layout */
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#define GPMC_NAND_ECC_LP_x16_LAYOUT {\
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.eccbytes = 12,\
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.eccpos = {2, 3, 4, 5, 6, 7, 8, 9,\
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10, 11, 12, 13},\
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.oobfree = {\
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{.offset = 60,\
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.length = 2 } } \
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}
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/** Small Page x8 NAND device Layout */
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#define GPMC_NAND_ECC_SP_x8_LAYOUT {\
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.eccbytes = 3,\
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.eccpos = {1, 2, 3},\
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.oobfree = {\
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{.offset = 14,\
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.length = 2 } } \
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}
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/** Small Page x16 NAND device Layout */
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#define GPMC_NAND_ECC_SP_x16_LAYOUT {\
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.eccbytes = 3,\
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.eccpos = {2, 3, 4},\
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.oobfree = {\
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{.offset = 14,\
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.length = 2 } } \
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}
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#endif /* CONFIG_NAND_OMAP_GPMC_HWECC */
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#endif /* __ASM_OMAP_NAND_GPMC_H */
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