66 lines
2.1 KiB
Plaintext
66 lines
2.1 KiB
Plaintext
/* This document is intended to provide the developer with information
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* how to integrate a new CPU (MACH) into this part of the barebox tree
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*/
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/** @page dev_mips_mach MIPS based CPU (MACH) into the tree
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@section mach_mips_reset What's happens when the reset signal is gone
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Barebox normally must be linked to RAM region, cached region KSEG0 is preferred.
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This make possible to run fast (because cache used) and skip MMU support.
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After reset MIPS CPU starting to fetch instructions from 0xBFC00000.
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@note Code running immediately after reset runs at an address it is not linked
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to: "runtime address != link address". You should only use branches and
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do not refer to fixed data. This implies the use of assembler code only.
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After MIPS CPU reset cache and MMU are in random state. They are unusable.
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barebox MIPS initialisation sequence:
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* set the CP0 STATUS register to some known and sensible state.
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Now you can load and store reliably in uncached space.
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* call a function \<mach_init_lowlevel\> (if not disabled).
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do some special things required only on specific CPU
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(e. g. init RAM controller, disable watchdog)
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* call a function \<board_init_lowlevel\> (if not disable).
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do some special things required only on specific board
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(e. g. setup GPIO to required state).
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** It is desirable to have some debug code to make some contact
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with the outside world from assembler code
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(e.g. debug_ll-like functions to write to rs232 console).
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* check integrity of barebox RAM execute location;
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* copy barebox to RAM execute location;
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* configure cache;
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* setup stack;
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** after this point you can call a standard C routine.
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* setup exception vectors in RAM;
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* setup CP0 STATUS to switch exception vector address to RAM;
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* call start_barebox()
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Further reading:
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* Dominic Sweetman, See MIPS Run, Morgan Kaufmann, 2nd edition, 2006
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ISBN-13: 978-0120884216
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@subsection mach_mips_malta_info Malta boards
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@li @subpage dev_malta_mach
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@subsection mach_bcm47xx_info BCM47xx-based boards
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@li @subpage dev_bcm47xx_mach
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@subsection mach_xburst_info XBurst-based boards
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@li @subpage dev_xburst_mach
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*/
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