164 lines
3.6 KiB
C
164 lines
3.6 KiB
C
#include <common.h>
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#include <asm/io.h>
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#include <asm-generic/div64.h>
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#include <mach/imx51-regs.h>
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#include "mach/clock-imx51.h"
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static u32 ccm_readl(u32 ofs)
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{
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return readl(MX51_CCM_BASE_ADDR + ofs);
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}
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static unsigned long ckil_get_rate(void)
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{
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return 32768;
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}
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static unsigned long osc_get_rate(void)
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{
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return 24000000;
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}
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static unsigned long fpm_get_rate(void)
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{
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return ckil_get_rate() * 512;
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}
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static unsigned long pll_get_rate(void __iomem *pllbase)
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{
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long mfi, mfn, mfd, pdf, ref_clk, mfn_abs;
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unsigned long dp_op, dp_mfd, dp_mfn, dp_ctl, pll_hfsm, dbl;
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u64 temp;
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unsigned long parent_rate;
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dp_ctl = readl(pllbase + MX51_PLL_DP_CTL);
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if ((dp_ctl & MX51_PLL_DP_CTL_REF_CLK_SEL_MASK) == 0)
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parent_rate = fpm_get_rate();
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else
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parent_rate = osc_get_rate();
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pll_hfsm = dp_ctl & MX51_PLL_DP_CTL_HFSM;
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dbl = dp_ctl & MX51_PLL_DP_CTL_DPDCK0_2_EN;
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if (pll_hfsm == 0) {
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dp_op = readl(pllbase + MX51_PLL_DP_OP);
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dp_mfd = readl(pllbase + MX51_PLL_DP_MFD);
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dp_mfn = readl(pllbase + MX51_PLL_DP_MFN);
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} else {
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dp_op = readl(pllbase + MX51_PLL_DP_HFS_OP);
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dp_mfd = readl(pllbase + MX51_PLL_DP_HFS_MFD);
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dp_mfn = readl(pllbase + MX51_PLL_DP_HFS_MFN);
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}
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pdf = dp_op & MX51_PLL_DP_OP_PDF_MASK;
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mfi = (dp_op & MX51_PLL_DP_OP_MFI_MASK) >> MX51_PLL_DP_OP_MFI_OFFSET;
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mfi = (mfi <= 5) ? 5 : mfi;
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mfd = dp_mfd & MX51_PLL_DP_MFD_MASK;
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mfn = mfn_abs = dp_mfn & MX51_PLL_DP_MFN_MASK;
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/* Sign extend to 32-bits */
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if (mfn >= 0x04000000) {
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mfn |= 0xFC000000;
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mfn_abs = -mfn;
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}
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ref_clk = 2 * parent_rate;
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if (dbl != 0)
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ref_clk *= 2;
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ref_clk /= (pdf + 1);
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temp = (u64)ref_clk * mfn_abs;
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do_div(temp, mfd + 1);
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if (mfn < 0)
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temp = -temp;
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temp = (ref_clk * mfi) + temp;
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return temp;
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}
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static unsigned long pll1_main_get_rate(void)
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{
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return pll_get_rate((void __iomem *)MX51_PLL1_BASE_ADDR);
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}
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static unsigned long pll2_sw_get_rate(void)
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{
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return pll_get_rate((void __iomem *)MX51_PLL2_BASE_ADDR);
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}
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static unsigned long pll3_sw_get_rate(void)
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{
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return pll_get_rate((void __iomem *)MX51_PLL3_BASE_ADDR);
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}
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unsigned long imx_get_uartclk(void)
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{
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u32 reg, prediv, podf;
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unsigned long parent_rate;
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parent_rate = pll2_sw_get_rate();
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reg = ccm_readl(MX51_CCM_CSCDR1);
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prediv = ((reg & MX51_CCM_CSCDR1_UART_CLK_PRED_MASK) >>
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MX51_CCM_CSCDR1_UART_CLK_PRED_OFFSET) + 1;
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podf = ((reg & MX51_CCM_CSCDR1_UART_CLK_PODF_MASK) >>
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MX51_CCM_CSCDR1_UART_CLK_PODF_OFFSET) + 1;
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return parent_rate / (prediv * podf);
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}
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static unsigned long imx_get_ahbclk(void)
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{
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u32 reg, div;
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reg = ccm_readl(MX51_CCM_CBCDR);
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div = ((reg >> 10) & 0x7) + 1;
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return pll2_sw_get_rate() / div;
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}
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unsigned long imx_get_ipgclk(void)
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{
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u32 reg, div;
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reg = ccm_readl(MX51_CCM_CBCDR);
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div = ((reg >> 8) & 0x3) + 1;
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return imx_get_ahbclk() / div;
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}
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unsigned long imx_get_gptclk(void)
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{
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return imx_get_ipgclk();
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}
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unsigned long imx_get_fecclk(void)
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{
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return imx_get_ipgclk();
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}
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unsigned long imx_get_mmcclk(void)
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{
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u32 reg, prediv, podf, rate;
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reg = ccm_readl(MX51_CCM_CSCDR1);
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prediv = ((reg & MX51_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK) >>
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MX51_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET) + 1;
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podf = ((reg & MX51_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK) >>
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MX51_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET) + 1;
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rate = pll2_sw_get_rate() / (prediv * podf);
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return rate;
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}
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void imx_dump_clocks(void)
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{
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printf("pll1: %ld\n", pll1_main_get_rate());
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printf("pll2: %ld\n", pll2_sw_get_rate());
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printf("pll3: %ld\n", pll3_sw_get_rate());
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printf("uart: %ld\n", imx_get_uartclk());
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printf("ipg: %ld\n", imx_get_ipgclk());
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printf("fec: %ld\n", imx_get_fecclk());
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printf("gpt: %ld\n", imx_get_gptclk());
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}
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