399 lines
9.5 KiB
C
399 lines
9.5 KiB
C
/*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <common.h>
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#include <init.h>
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#include <io.h>
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#include <linux/mtd/nand.h>
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#include <asm/cache.h>
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#include <asm/sections.h>
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#include <asm/barebox-arm.h>
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#include <asm/barebox-arm-head.h>
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#include <mach/imx-nand.h>
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#include <mach/esdctl.h>
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#include <mach/generic.h>
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#include <mach/imx21-regs.h>
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#include <mach/imx25-regs.h>
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#include <mach/imx27-regs.h>
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#include <mach/imx31-regs.h>
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#include <mach/imx35-regs.h>
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static void __bare_init noinline imx_nandboot_wait_op_done(void *regs)
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{
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u32 r;
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while (1) {
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r = readw(regs + NFC_V1_V2_CONFIG2);
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if (r & NFC_V1_V2_CONFIG2_INT)
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break;
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};
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r &= ~NFC_V1_V2_CONFIG2_INT;
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writew(r, regs + NFC_V1_V2_CONFIG2);
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}
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/*
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* This function issues the specified command to the NAND device and
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* waits for completion.
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*
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* @param cmd command for NAND Flash
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*/
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static void __bare_init imx_nandboot_send_cmd(void *regs, u16 cmd)
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{
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writew(cmd, regs + NFC_V1_V2_FLASH_CMD);
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writew(NFC_CMD, regs + NFC_V1_V2_CONFIG2);
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imx_nandboot_wait_op_done(regs);
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}
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/*
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* This function sends an address (or partial address) to the
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* NAND device. The address is used to select the source/destination for
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* a NAND command.
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*
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* @param addr address to be written to NFC.
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* @param islast True if this is the last address cycle for command
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*/
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static void __bare_init noinline imx_nandboot_send_addr(void *regs, u16 addr)
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{
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writew(addr, regs + NFC_V1_V2_FLASH_ADDR);
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writew(NFC_ADDR, regs + NFC_V1_V2_CONFIG2);
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/* Wait for operation to complete */
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imx_nandboot_wait_op_done(regs);
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}
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static void __bare_init imx_nandboot_nfc_addr(void *regs, u32 offs, int pagesize_2k)
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{
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imx_nandboot_send_addr(regs, offs & 0xff);
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if (pagesize_2k) {
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imx_nandboot_send_addr(regs, offs & 0xff);
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imx_nandboot_send_addr(regs, (offs >> 11) & 0xff);
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imx_nandboot_send_addr(regs, (offs >> 19) & 0xff);
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imx_nandboot_send_addr(regs, (offs >> 27) & 0xff);
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imx_nandboot_send_cmd(regs, NAND_CMD_READSTART);
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} else {
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imx_nandboot_send_addr(regs, (offs >> 9) & 0xff);
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imx_nandboot_send_addr(regs, (offs >> 17) & 0xff);
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imx_nandboot_send_addr(regs, (offs >> 25) & 0xff);
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}
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}
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static void __bare_init imx_nandboot_send_page(void *regs,
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unsigned int ops, int pagesize_2k)
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{
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int bufs, i;
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if (nfc_is_v1() && pagesize_2k)
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bufs = 4;
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else
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bufs = 1;
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for (i = 0; i < bufs; i++) {
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/* NANDFC buffer 0 is used for page read/write */
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writew(i, regs + NFC_V1_V2_BUF_ADDR);
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writew(ops, regs + NFC_V1_V2_CONFIG2);
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/* Wait for operation to complete */
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imx_nandboot_wait_op_done(regs);
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}
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}
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static void __bare_init __memcpy32(void *trg, const void *src, int size)
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{
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int i;
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unsigned int *t = trg;
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unsigned const int *s = src;
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for (i = 0; i < (size >> 2); i++)
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*t++ = *s++;
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}
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static noinline void __bare_init imx_nandboot_get_page(void *regs,
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u32 offs, int pagesize_2k)
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{
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imx_nandboot_send_cmd(regs, NAND_CMD_READ0);
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imx_nandboot_nfc_addr(regs, offs, pagesize_2k);
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imx_nandboot_send_page(regs, NFC_OUTPUT, pagesize_2k);
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}
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void __bare_init imx_nand_load_image(void *dest, int size, void __iomem *base,
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int pagesize_2k)
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{
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u32 tmp, page, block, blocksize, pagesize, badblocks;
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int bbt = 0;
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void *regs, *spare0;
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if (pagesize_2k) {
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pagesize = 2048;
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blocksize = 128 * 1024;
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} else {
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pagesize = 512;
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blocksize = 16 * 1024;
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}
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if (nfc_is_v21()) {
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regs = base + 0x1e00;
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spare0 = base + 0x1000;
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} else if (nfc_is_v1()) {
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regs = base + 0xe00;
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spare0 = base + 0x800;
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}
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imx_nandboot_send_cmd(regs, NAND_CMD_RESET);
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/* preset operation */
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/* Unlock the internal RAM Buffer */
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writew(0x2, regs + NFC_V1_V2_CONFIG);
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/* Unlock Block Command for given address range */
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writew(0x4, regs + NFC_V1_V2_WRPROT);
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tmp = readw(regs + NFC_V1_V2_CONFIG1);
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tmp |= NFC_V1_V2_CONFIG1_ECC_EN;
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if (nfc_is_v21())
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/* currently no support for 218 byte OOB with stronger ECC */
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tmp |= NFC_V2_CONFIG1_ECC_MODE_4;
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tmp &= ~(NFC_V1_V2_CONFIG1_SP_EN | NFC_V1_V2_CONFIG1_INT_MSK);
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writew(tmp, regs + NFC_V1_V2_CONFIG1);
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if (nfc_is_v21()) {
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if (pagesize_2k)
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writew(NFC_V2_SPAS_SPARESIZE(64), regs + NFC_V2_SPAS);
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else
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writew(NFC_V2_SPAS_SPARESIZE(16), regs + NFC_V2_SPAS);
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}
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/*
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* Check if this image has a bad block table embedded. See
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* imx_bbu_external_nand_register_handler for more information
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*/
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badblocks = *(uint32_t *)(base + ARM_HEAD_SPARE_OFS);
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if (badblocks == IMX_NAND_BBT_MAGIC) {
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bbt = 1;
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badblocks = *(uint32_t *)(base + ARM_HEAD_SPARE_OFS + 4);
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}
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block = page = 0;
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while (1) {
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page = 0;
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imx_nandboot_get_page(regs, block * blocksize +
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page * pagesize, pagesize_2k);
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if (bbt) {
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if (badblocks & (1 << block)) {
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block++;
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continue;
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}
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} else if (pagesize_2k) {
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if ((readw(spare0) & 0xff) != 0xff) {
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block++;
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continue;
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}
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} else {
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if ((readw(spare0 + 4) & 0xff00) != 0xff00) {
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block++;
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continue;
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}
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}
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while (page * pagesize < blocksize) {
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debug("page: %d block: %d dest: %p src "
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"0x%08x\n",
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page, block, dest,
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block * blocksize +
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page * pagesize);
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if (page)
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imx_nandboot_get_page(regs, block * blocksize +
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page * pagesize, pagesize_2k);
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page++;
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__memcpy32(dest, base, pagesize);
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dest += pagesize;
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size -= pagesize;
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if (size <= 0)
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return;
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}
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block++;
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}
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}
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/*
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* This function assumes the currently running binary has been
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* copied from its current position to an offset. It returns
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* to the calling function - offset.
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* NOTE: The calling function may not return itself since it still
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* works on the old content of the lr register. Only call this
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* from a __noreturn function.
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*/
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static __bare_init __naked void jump_sdram(unsigned long offset)
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{
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flush_icache();
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__asm__ __volatile__ (
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"sub lr, lr, %0;"
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"mov pc, lr;" : : "r"(offset)
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);
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}
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/*
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* Load and start barebox from NAND. This function also checks if we are really
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* running inside the NFC address space. If not, barebox is started from the
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* currently running address without loading anything from NAND.
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*/
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int __bare_init imx_barebox_boot_nand_external(unsigned long nfc_base)
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{
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u32 r;
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u32 *src, *trg;
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int i;
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/* skip NAND boot if not running from NFC space */
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r = get_pc();
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if (r < nfc_base || r > nfc_base + 0x800)
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return 0;
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src = (unsigned int *)nfc_base;
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trg = (unsigned int *)ld_var(_text);
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/* Move ourselves out of NFC SRAM */
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for (i = 0; i < 0x800 / sizeof(int); i++)
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*trg++ = *src++;
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return 1;
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}
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#define BARE_INIT_FUNCTION(name) \
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void __noreturn __section(.text_bare_init_##name) \
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name
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/*
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* SoC specific entries for booting in external NAND mode. To be called from
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* the board specific entry code. This is safe to call even if not booting from
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* NAND. In this case the booting is continued without loading an image from
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* NAND. This function needs a stack to be set up.
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*/
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#ifdef BROKEN
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BARE_INIT_FUNCTION(imx21_barebox_boot_nand_external)(void)
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{
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unsigned long nfc_base = MX21_NFC_BASE_ADDR;
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int pagesize_2k;
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if (imx_barebox_boot_nand_external(nfc_base)) {
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jump_sdram(nfc_base - ld_var(_text));
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if (readl(MX21_SYSCTRL_BASE_ADDR + 0x14) & (1 << 5))
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pagesize_2k = 1;
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else
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pagesize_2k = 0;
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imx_nand_load_image((void *)ld_var(_text),
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ld_var(barebox_image_size),
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(void *)nfc_base, pagesize_2k);
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}
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/* This function doesn't exist yet */
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imx21_barebox_entry(0);
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}
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#endif
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BARE_INIT_FUNCTION(imx25_barebox_boot_nand_external)(void)
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{
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unsigned long nfc_base = MX25_NFC_BASE_ADDR;
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int pagesize_2k;
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if (imx_barebox_boot_nand_external(nfc_base)) {
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jump_sdram(nfc_base - ld_var(_text));
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if (readl(MX25_CCM_BASE_ADDR + MX25_CCM_RCSR) & (1 << 8))
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pagesize_2k = 1;
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else
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pagesize_2k = 0;
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imx_nand_load_image((void *)ld_var(_text),
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ld_var(_barebox_image_size),
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(void *)nfc_base, pagesize_2k);
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}
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imx25_barebox_entry(0);
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}
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BARE_INIT_FUNCTION(imx27_barebox_boot_nand_external)(void)
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{
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unsigned long nfc_base = MX27_NFC_BASE_ADDR;
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int pagesize_2k;
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if (imx_barebox_boot_nand_external(nfc_base)) {
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jump_sdram(nfc_base - ld_var(_text));
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if (readl(MX27_SYSCTRL_BASE_ADDR + 0x14) & (1 << 5))
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pagesize_2k = 1;
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else
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pagesize_2k = 0;
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imx_nand_load_image((void *)ld_var(_text),
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ld_var(_barebox_image_size),
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(void *)nfc_base, pagesize_2k);
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}
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imx27_barebox_entry(0);
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}
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BARE_INIT_FUNCTION(imx31_barebox_boot_nand_external)(void)
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{
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unsigned long nfc_base = MX31_NFC_BASE_ADDR;
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int pagesize_2k;
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if (imx_barebox_boot_nand_external(nfc_base)) {
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jump_sdram(nfc_base - ld_var(_text));
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if (readl(MX31_CCM_BASE_ADDR + MX31_CCM_RCSR) & MX31_RCSR_NFMS)
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pagesize_2k = 1;
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else
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pagesize_2k = 0;
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imx_nand_load_image((void *)ld_var(_text),
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ld_var(_barebox_image_size),
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(void *)nfc_base, pagesize_2k);
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}
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imx31_barebox_entry(0);
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}
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BARE_INIT_FUNCTION(imx35_barebox_boot_nand_external)(void)
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{
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unsigned long nfc_base = MX35_NFC_BASE_ADDR;
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int pagesize_2k;
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if (imx_barebox_boot_nand_external(nfc_base)) {
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jump_sdram(nfc_base - ld_var(_text));
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if (readl(MX35_CCM_BASE_ADDR + MX35_CCM_RCSR) & (1 << 8))
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pagesize_2k = 1;
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else
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pagesize_2k = 0;
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imx_nand_load_image((void *)ld_var(_text),
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ld_var(_barebox_image_size),
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(void *)nfc_base, pagesize_2k);
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}
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imx35_barebox_entry(0);
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}
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