670 lines
17 KiB
C
670 lines
17 KiB
C
/*
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* Cirrus Logic EP93xx ethernet MAC / MII driver.
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*
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* Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
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*
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* Copyright (C) 2004, 2005
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* Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
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*
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* Based on the original eth.[ch] Cirrus Logic EP93xx Rev D. Ethernet Driver,
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* which is
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*
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* (C) Copyright 2002 2003
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* Adam Bezanson, Network Audio Technologies, Inc.
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* <bezanson@netaudiotech.com>
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*
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* See file CREDITS for list of people who contributed to this project.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <common.h>
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#include <command.h>
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#include <init.h>
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#include <malloc.h>
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#include <miidev.h>
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#include <io.h>
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#include <linux/types.h>
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#include <mach/ep93xx-regs.h>
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#include "ep93xx.h"
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#define EP93XX_MAX_PKT_SIZE 1536
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static int ep93xx_phy_read(struct mii_device *mdev, int phy_addr, int phy_reg);
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static int ep93xx_phy_write(struct mii_device *mdev, int phy_addr, int phy_reg,
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int value);
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static inline struct ep93xx_eth_priv *ep93xx_get_priv(struct eth_device *edev)
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{
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return (struct ep93xx_eth_priv *)edev->priv;
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}
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static inline struct mac_regs *ep93xx_get_regs(struct eth_device *edev)
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{
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struct ep93xx_eth_priv *priv = ep93xx_get_priv(edev);
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return priv->regs;
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}
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#if defined(EP93XX_MAC_DEBUG)
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/**
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* Dump ep93xx_mac values to the terminal.
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*/
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static void dump_dev(struct eth_device *edev)
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{
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struct ep93xx_eth_priv *priv = ep93xx_get_priv(edev);
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int i;
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printf("\ndump_dev()\n");
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printf(" rx_dq.base %p\n", priv->rx_dq.base);
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printf(" rx_dq.current %p\n", priv->rx_dq.current);
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printf(" rx_dq.end %p\n", priv->rx_dq.end);
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printf(" rx_sq.base %p\n", priv->rx_sq.base);
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printf(" rx_sq.current %p\n", priv->rx_sq.current);
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printf(" rx_sq.end %p\n", priv->rx_sq.end);
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for (i = 0; i < NUMRXDESC; i++)
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printf(" rx_buffer[%2.d] %p\n", i, NetRxPackets[i]);
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printf(" tx_dq.base %p\n", priv->tx_dq.base);
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printf(" tx_dq.current %p\n", priv->tx_dq.current);
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printf(" tx_dq.end %p\n", priv->tx_dq.end);
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printf(" tx_sq.base %p\n", priv->tx_sq.base);
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printf(" tx_sq.current %p\n", priv->tx_sq.current);
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printf(" tx_sq.end %p\n", priv->tx_sq.end);
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}
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/**
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* Dump all RX descriptor queue entries to the terminal.
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*/
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static void dump_rx_descriptor_queue(struct eth_device *edev)
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{
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struct ep93xx_eth_priv *priv = ep93xx_get_priv(edev);
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int i;
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printf("\ndump_rx_descriptor_queue()\n");
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printf(" descriptor address word1 word2\n");
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for (i = 0; i < NUMRXDESC; i++) {
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printf(" [ %p ] %08X %08X\n",
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priv->rx_dq.base + i,
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(priv->rx_dq.base + i)->word1,
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(priv->rx_dq.base + i)->word2);
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}
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}
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/**
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* Dump all RX status queue entries to the terminal.
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*/
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static void dump_rx_status_queue(struct eth_device *edev)
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{
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struct ep93xx_eth_priv *priv = ep93xx_get_priv(edev);
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int i;
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printf("\ndump_rx_status_queue()\n");
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printf(" descriptor address word1 word2\n");
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for (i = 0; i < NUMRXDESC; i++) {
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printf(" [ %p ] %08X %08X\n",
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priv->rx_sq.base + i,
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(priv->rx_sq.base + i)->word1,
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(priv->rx_sq.base + i)->word2);
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}
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}
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/**
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* Dump all TX descriptor queue entries to the terminal.
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*/
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static void dump_tx_descriptor_queue(struct eth_device *edev)
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{
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struct ep93xx_eth_priv *priv = ep93xx_get_priv(edev);
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int i;
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printf("\ndump_tx_descriptor_queue()\n");
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printf(" descriptor address word1 word2\n");
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for (i = 0; i < NUMTXDESC; i++) {
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printf(" [ %p ] %08X %08X\n",
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priv->tx_dq.base + i,
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(priv->tx_dq.base + i)->word1,
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(priv->tx_dq.base + i)->word2);
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}
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}
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/**
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* Dump all TX status queue entries to the terminal.
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*/
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static void dump_tx_status_queue(struct eth_device *edev)
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{
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struct ep93xx_eth_priv *priv = ep93xx_get_priv(edev);
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int i;
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printf("\ndump_tx_status_queue()\n");
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printf(" descriptor address word1\n");
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for (i = 0; i < NUMTXDESC; i++) {
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printf(" [ %p ] %08X\n",
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priv->rx_sq.base + i,
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(priv->rx_sq.base + i)->word1);
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}
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}
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#else
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#define dump_dev(x)
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#define dump_rx_descriptor_queue(x)
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#define dump_rx_status_queue(x)
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#define dump_tx_descriptor_queue(x)
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#define dump_tx_status_queue(x)
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#endif /* defined(EP93XX_MAC_DEBUG) */
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/**
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* Reset the EP93xx MAC by twiddling the soft reset bit and spinning until
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* it's cleared.
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*/
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static void ep93xx_eth_reset(struct eth_device *edev)
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{
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struct mac_regs *regs = ep93xx_get_regs(edev);
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uint32_t value;
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pr_debug("+ep93xx_eth_reset\n");
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value = readl(®s->selfctl);
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value |= SELFCTL_RESET;
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writel(value, ®s->selfctl);
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while (readl(®s->selfctl) & SELFCTL_RESET)
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; /* noop */
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pr_debug("-ep93xx_eth_reset\n");
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}
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static int ep93xx_eth_init_dev(struct eth_device *edev)
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{
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pr_debug("+ep93xx_eth_init_dev\n");
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pr_debug("-ep93xx_eth_init_dev\n");
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return 0;
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}
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static int ep93xx_eth_open(struct eth_device *edev)
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{
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struct ep93xx_eth_priv *priv = ep93xx_get_priv(edev);
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struct mac_regs *regs = ep93xx_get_regs(edev);
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int i;
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pr_debug("+ep93xx_eth_open\n");
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ep93xx_eth_reset(edev);
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/* Reset the descriptor queues' current and end address values */
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priv->tx_dq.current = priv->tx_dq.base;
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priv->tx_dq.end = (priv->tx_dq.base + NUMTXDESC);
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priv->tx_sq.current = priv->tx_sq.base;
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priv->tx_sq.end = (priv->tx_sq.base + NUMTXDESC);
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priv->rx_dq.current = priv->rx_dq.base;
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priv->rx_dq.end = (priv->rx_dq.base + NUMRXDESC);
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priv->rx_sq.current = priv->rx_sq.base;
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priv->rx_sq.end = (priv->rx_sq.base + NUMRXDESC);
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/*
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* Set the transmit descriptor and status queues' base address,
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* current address, and length registers. Set the maximum frame
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* length and threshold. Enable the transmit descriptor processor.
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*/
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writel((uint32_t)priv->tx_dq.base, ®s->txdq.badd);
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writel((uint32_t)priv->tx_dq.base, ®s->txdq.curadd);
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writel(sizeof(struct tx_descriptor) * NUMTXDESC, ®s->txdq.blen);
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writel((uint32_t)priv->tx_sq.base, ®s->txstsq.badd);
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writel((uint32_t)priv->tx_sq.base, ®s->txstsq.curadd);
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writel(sizeof(struct tx_status) * NUMTXDESC, ®s->txstsq.blen);
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writel(0x00040000, ®s->txdthrshld);
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writel(0x00040000, ®s->txststhrshld);
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writel((TXSTARTMAX << 0) | (EP93XX_MAX_PKT_SIZE << 16), ®s->maxfrmlen);
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writel(BMCTL_TXEN, ®s->bmctl);
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/*
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* Set the receive descriptor and status queues' base address,
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* current address, and length registers. Enable the receive
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* descriptor processor.
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*/
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writel((uint32_t)priv->rx_dq.base, ®s->rxdq.badd);
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writel((uint32_t)priv->rx_dq.base, ®s->rxdq.curadd);
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writel(sizeof(struct rx_descriptor) * NUMRXDESC, ®s->rxdq.blen);
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writel((uint32_t)priv->rx_sq.base, ®s->rxstsq.badd);
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writel((uint32_t)priv->rx_sq.base, ®s->rxstsq.curadd);
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writel(sizeof(struct rx_status) * NUMRXDESC, ®s->rxstsq.blen);
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writel(0x00040000, ®s->rxdthrshld);
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writel(BMCTL_RXEN, ®s->bmctl);
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writel(0x00040000, ®s->rxststhrshld);
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/* Wait until the receive descriptor processor is active */
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while (!(readl(®s->bmsts) & BMSTS_RXACT))
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; /* noop */
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/*
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* Initialize the RX descriptor queue. Clear the TX descriptor queue.
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* Clear the RX and TX status queues. Enqueue the RX descriptor and
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* status entries to the MAC.
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*/
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for (i = 0; i < NUMRXDESC; i++) {
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/* set buffer address */
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(priv->rx_dq.base + i)->word1 = (uint32_t)NetRxPackets[i];
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/* set buffer length, clear buffer index and NSOF */
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(priv->rx_dq.base + i)->word2 = EP93XX_MAX_PKT_SIZE;
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}
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memset(priv->tx_dq.base, 0,
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(sizeof(struct tx_descriptor) * NUMTXDESC));
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memset(priv->rx_sq.base, 0,
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(sizeof(struct rx_status) * NUMRXDESC));
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memset(priv->tx_sq.base, 0,
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(sizeof(struct tx_status) * NUMTXDESC));
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writel(NUMRXDESC, ®s->rxdqenq);
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writel(NUMRXDESC, ®s->rxstsqenq);
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/* Turn on RX and TX */
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writel(RXCTL_IA0 | RXCTL_BA | RXCTL_SRXON |
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RXCTL_RCRCA | RXCTL_MA, ®s->rxctl);
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writel(TXCTL_STXON, ®s->txctl);
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/* Dump data structures if we're debugging */
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dump_dev(edev);
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dump_rx_descriptor_queue(edev);
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dump_rx_status_queue(edev);
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dump_tx_descriptor_queue(edev);
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dump_tx_status_queue(edev);
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pr_debug("-ep93xx_eth_open\n");
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return 0;
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}
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/**
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* Halt EP93xx MAC transmit and receive by clearing the TxCTL and RxCTL
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* registers.
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*/
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static void ep93xx_eth_halt(struct eth_device *edev)
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{
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struct mac_regs *regs = ep93xx_get_regs(edev);
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pr_debug("+ep93xx_eth_halt\n");
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writel(0x00000000, ®s->rxctl);
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writel(0x00000000, ®s->txctl);
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pr_debug("-ep93xx_eth_halt\n");
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}
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/**
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* Copy a frame of data from the MAC into the protocol layer for further
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* processing.
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*/
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static int ep93xx_eth_rcv_packet(struct eth_device *edev)
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{
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struct ep93xx_eth_priv *priv = ep93xx_get_priv(edev);
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struct mac_regs *regs = ep93xx_get_regs(edev);
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int ret = -1;
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pr_debug("+ep93xx_eth_rcv_packet\n");
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if (RX_STATUS_RFP(priv->rx_sq.current)) {
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if (RX_STATUS_RWE(priv->rx_sq.current)) {
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/*
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* We have a good frame. Extract the frame's length
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* from the current rx_status_queue entry, and copy
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* the frame's data into NetRxPackets[] of the
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* protocol stack. We track the total number of
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* bytes in the frame (nbytes_frame) which will be
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* used when we pass the data off to the protocol
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* layer via net_receive().
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*/
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net_receive((uchar *)priv->rx_dq.current->word1,
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RX_STATUS_FRAME_LEN(priv->rx_sq.current));
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pr_debug("reporting %d bytes...\n",
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RX_STATUS_FRAME_LEN(priv->rx_sq.current));
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ret = 0;
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} else {
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/* Do we have an erroneous packet? */
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pr_err("packet rx error, status %08X %08X\n",
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priv->rx_sq.current->word1,
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priv->rx_sq.current->word2);
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dump_rx_descriptor_queue(edev);
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dump_rx_status_queue(edev);
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}
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/*
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* Clear the associated status queue entry, and
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* increment our current pointers to the next RX
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* descriptor and status queue entries (making sure
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* we wrap properly).
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*/
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memset((void *)priv->rx_sq.current, 0,
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sizeof(struct rx_status));
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priv->rx_sq.current++;
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if (priv->rx_sq.current >= priv->rx_sq.end)
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priv->rx_sq.current = priv->rx_sq.base;
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priv->rx_dq.current++;
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if (priv->rx_dq.current >= priv->rx_dq.end)
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priv->rx_dq.current = priv->rx_dq.base;
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/*
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* Finally, return the RX descriptor and status entries
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* back to the MAC engine, and loop again, checking for
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* more descriptors to process.
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*/
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writel(1, ®s->rxdqenq);
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writel(1, ®s->rxstsqenq);
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} else {
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ret = 0;
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}
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pr_debug("-ep93xx_eth_rcv_packet %d\n", ret);
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return ret;
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}
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/**
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* Send a block of data via ethernet.
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*/
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static int ep93xx_eth_send_packet(struct eth_device *edev,
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void *packet, int length)
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{
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struct ep93xx_eth_priv *priv = ep93xx_get_priv(edev);
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struct mac_regs *regs = ep93xx_get_regs(edev);
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int ret = -1;
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pr_debug("+ep93xx_eth_send_packet\n");
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/*
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* Initialize the TX descriptor queue with the new packet's info.
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* Clear the associated status queue entry. Enqueue the packet
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* to the MAC for transmission.
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*/
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/* set buffer address */
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priv->tx_dq.current->word1 = (uint32_t)packet;
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/* set buffer length and EOF bit */
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priv->tx_dq.current->word2 = length | TX_DESC_EOF;
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/* clear tx status */
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priv->tx_sq.current->word1 = 0;
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/* enqueue the TX descriptor */
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writel(1, ®s->txdqenq);
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/* wait for the frame to become processed */
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while (!TX_STATUS_TXFP(priv->tx_sq.current))
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; /* noop */
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if (!TX_STATUS_TXWE(priv->tx_sq.current)) {
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pr_err("packet tx error, status %08X\n",
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priv->tx_sq.current->word1);
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dump_tx_descriptor_queue(edev);
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dump_tx_status_queue(edev);
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/* TODO: Add better error handling? */
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goto eth_send_failed_0;
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}
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ret = 0;
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/* Fall through */
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eth_send_failed_0:
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pr_debug("-ep93xx_eth_send_packet %d\n", ret);
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return ret;
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}
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static int ep93xx_eth_get_ethaddr(struct eth_device *edev,
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unsigned char *mac_addr)
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{
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struct mac_regs *regs = ep93xx_get_regs(edev);
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uint32_t value;
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value = readl(®s->indad);
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mac_addr[0] = value & 0xFF;
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mac_addr[1] = (value >> 8) & 0xFF;
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mac_addr[2] = (value >> 16) & 0xFF;
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mac_addr[3] = (value >> 24) & 0xFF;
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value = readl(®s->indad_upper);
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mac_addr[4] = value & 0xFF;
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mac_addr[5] = (value >> 8) & 0xFF;
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return 0;
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}
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static int ep93xx_eth_set_ethaddr(struct eth_device *edev,
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unsigned char *mac_addr)
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{
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struct mac_regs *regs = ep93xx_get_regs(edev);
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writel(AFP_IAPRIMARY, ®s->afp);
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writel(mac_addr[0] | (mac_addr[1] << 8) |
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(mac_addr[2] << 16) | (mac_addr[3] << 24),
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®s->indad);
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writel(mac_addr[4] | (mac_addr[5] << 8), ®s->indad_upper);
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return 0;
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}
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static int ep93xx_eth_probe(struct device_d *dev)
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{
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struct eth_device *edev;
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struct ep93xx_eth_priv *priv;
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int ret = -1;
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pr_debug("ep93xx_eth_probe()\n");
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edev = xzalloc(sizeof(struct eth_device) +
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sizeof(struct ep93xx_eth_priv));
|
|
dev->type_data = edev;
|
|
edev->priv = (struct ep93xx_eth_priv *)(edev + 1);
|
|
|
|
priv = edev->priv;
|
|
priv->regs = (struct mac_regs *)MAC_BASE;
|
|
|
|
edev->init = ep93xx_eth_init_dev;
|
|
edev->open = ep93xx_eth_open;
|
|
edev->send = ep93xx_eth_send_packet;
|
|
edev->recv = ep93xx_eth_rcv_packet;
|
|
edev->halt = ep93xx_eth_halt;
|
|
edev->get_ethaddr = ep93xx_eth_get_ethaddr;
|
|
edev->set_ethaddr = ep93xx_eth_set_ethaddr;
|
|
edev->parent = dev;
|
|
|
|
priv->miidev.read = ep93xx_phy_read;
|
|
priv->miidev.write = ep93xx_phy_write;
|
|
priv->miidev.address = 0;
|
|
priv->miidev.flags = 0;
|
|
priv->miidev.parent = dev;
|
|
|
|
priv->tx_dq.base = calloc(NUMTXDESC,
|
|
sizeof(struct tx_descriptor));
|
|
if (priv->tx_dq.base == NULL) {
|
|
pr_err("calloc() failed: tx_dq.base");
|
|
goto eth_probe_failed_0;
|
|
}
|
|
|
|
priv->tx_sq.base = calloc(NUMTXDESC,
|
|
sizeof(struct tx_status));
|
|
if (priv->tx_sq.base == NULL) {
|
|
pr_err("calloc() failed: tx_sq.base");
|
|
goto eth_probe_failed_1;
|
|
}
|
|
|
|
priv->rx_dq.base = calloc(NUMRXDESC,
|
|
sizeof(struct rx_descriptor));
|
|
if (priv->rx_dq.base == NULL) {
|
|
pr_err("calloc() failed: rx_dq.base");
|
|
goto eth_probe_failed_2;
|
|
}
|
|
|
|
priv->rx_sq.base = calloc(NUMRXDESC,
|
|
sizeof(struct rx_status));
|
|
if (priv->rx_sq.base == NULL) {
|
|
pr_err("calloc() failed: rx_sq.base");
|
|
goto eth_probe_failed_3;
|
|
}
|
|
|
|
mii_register(&priv->miidev);
|
|
eth_register(edev);
|
|
|
|
ret = 0;
|
|
|
|
goto eth_probe_done;
|
|
|
|
eth_probe_failed_3:
|
|
free(priv->rx_dq.base);
|
|
/* Fall through */
|
|
|
|
eth_probe_failed_2:
|
|
free(priv->tx_sq.base);
|
|
/* Fall through */
|
|
|
|
eth_probe_failed_1:
|
|
free(priv->tx_dq.base);
|
|
/* Fall through */
|
|
|
|
eth_probe_failed_0:
|
|
/* Fall through */
|
|
|
|
eth_probe_done:
|
|
return ret;
|
|
}
|
|
|
|
/* -----------------------------------------------------------------------------
|
|
* EP93xx ethernet MII functionality.
|
|
*/
|
|
|
|
/**
|
|
* Maximum MII address we support
|
|
*/
|
|
#define MII_ADDRESS_MAX 31
|
|
|
|
/**
|
|
* Maximum MII register address we support
|
|
*/
|
|
#define MII_REGISTER_MAX 31
|
|
|
|
/**
|
|
* Read a 16-bit value from an MII register.
|
|
*/
|
|
static int ep93xx_phy_read(struct mii_device *mdev, int phy_addr, int phy_reg)
|
|
{
|
|
struct mac_regs *regs = ep93xx_get_regs(mdev->edev);
|
|
int value = -1;
|
|
uint32_t self_ctl;
|
|
|
|
pr_debug("+ep93xx_phy_read\n");
|
|
|
|
/*
|
|
* Save the current SelfCTL register value. Set MAC to suppress
|
|
* preamble bits. Wait for any previous MII command to complete
|
|
* before issuing the new command.
|
|
*/
|
|
self_ctl = readl(®s->selfctl);
|
|
#if defined(CONFIG_MII_SUPPRESS_PREAMBLE) /* TODO */
|
|
writel(self_ctl & ~(1 << 8), ®s->selfctl);
|
|
#endif /* defined(CONFIG_MII_SUPPRESS_PREAMBLE) */
|
|
|
|
while (readl(®s->miists) & MIISTS_BUSY)
|
|
; /* noop */
|
|
|
|
/*
|
|
* Issue the MII 'read' command. Wait for the command to complete.
|
|
* Read the MII data value.
|
|
*/
|
|
writel(MIICMD_OPCODE_READ | ((uint32_t)phy_addr << 5) |
|
|
(uint32_t)phy_reg, ®s->miicmd);
|
|
while (readl(®s->miists) & MIISTS_BUSY)
|
|
; /* noop */
|
|
|
|
value = (unsigned short)readl(®s->miidata);
|
|
|
|
/* Restore the saved SelfCTL value and return. */
|
|
writel(self_ctl, ®s->selfctl);
|
|
|
|
pr_debug("-ep93xx_phy_read\n");
|
|
|
|
return value;
|
|
}
|
|
|
|
/**
|
|
* Write a 16-bit value to an MII register.
|
|
*/
|
|
static int ep93xx_phy_write(struct mii_device *mdev, int phy_addr,
|
|
int phy_reg, int value)
|
|
{
|
|
struct mac_regs *regs = ep93xx_get_regs(mdev->edev);
|
|
uint32_t self_ctl;
|
|
|
|
pr_debug("+ep93xx_phy_write\n");
|
|
|
|
/*
|
|
* Save the current SelfCTL register value. Set MAC to suppress
|
|
* preamble bits. Wait for any previous MII command to complete
|
|
* before issuing the new command.
|
|
*/
|
|
self_ctl = readl(®s->selfctl);
|
|
#if defined(CONFIG_MII_SUPPRESS_PREAMBLE) /* TODO */
|
|
writel(self_ctl & ~(1 << 8), ®s->selfctl);
|
|
#endif /* defined(CONFIG_MII_SUPPRESS_PREAMBLE) */
|
|
|
|
while (readl(®s->miists) & MIISTS_BUSY)
|
|
; /* noop */
|
|
|
|
/* Issue the MII 'write' command. Wait for the command to complete. */
|
|
writel((uint32_t)value, ®s->miidata);
|
|
writel(MIICMD_OPCODE_WRITE | ((uint32_t)phy_addr << 5) | phy_reg,
|
|
®s->miicmd);
|
|
while (readl(®s->miists) & MIISTS_BUSY)
|
|
; /* noop */
|
|
|
|
/* Restore the saved SelfCTL value and return. */
|
|
writel(self_ctl, ®s->selfctl);
|
|
|
|
pr_debug("-ep93xx_phy_write\n");
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct driver_d ep93xx_eth_driver = {
|
|
.name = "ep93xx_eth",
|
|
.probe = ep93xx_eth_probe,
|
|
};
|
|
|
|
static int ep93xx_eth_init(void)
|
|
{
|
|
register_driver(&ep93xx_eth_driver);
|
|
return 0;
|
|
}
|
|
|
|
device_initcall(ep93xx_eth_init);
|