175 lines
3.9 KiB
C
175 lines
3.9 KiB
C
/*
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* Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at)
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* Copyright (C) 2009-2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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*
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* Under GPLv2
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*/
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#include <common.h>
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#include <asm/system.h>
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#include <asm/barebox-arm.h>
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#include <asm/barebox-arm-head.h>
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#include <mach/hardware.h>
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#include <mach/at91_pmc.h>
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#include <mach/at91_pio.h>
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#include <mach/at91_rstc.h>
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#include <mach/at91_wdt.h>
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#include <mach/at91sam9_matrix.h>
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#include <mach/at91sam9_sdramc.h>
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#include <mach/at91sam9_smc.h>
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#include <mach/io.h>
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#include <init.h>
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static void inline access_sdram(void)
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{
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writel(0x00000000, AT91_SDRAM_BASE);
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}
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static void inline pmc_check_mckrdy(void)
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{
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u32 r;
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do {
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r = at91_sys_read(AT91_PMC_SR);
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} while (!(r & AT91_PMC_MCKRDY));
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}
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void __naked __bare_init reset(void)
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{
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u32 r;
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int i;
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common_reset();
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at91_sys_write(AT91_WDT_MR, CONFIG_SYS_WDTC_WDMR_VAL);
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/* configure PIOx as EBI0 D[16-31] */
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#ifdef CONFIG_ARCH_AT91SAM9263
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__raw_writel(CONFIG_SYS_PIOD_PDR_VAL1, AT91_BASE_PIOD + PIO_PDR);
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__raw_writel(CONFIG_SYS_PIOD_PPUDR_VAL, AT91_BASE_PIOD + PIO_PUDR);
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__raw_writel(CONFIG_SYS_PIOD_PPUDR_VAL, AT91_BASE_PIOD + PIO_ASR);
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#else
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__raw_writel(CONFIG_SYS_PIOC_PDR_VAL1, AT91_BASE_PIOC + PIO_PDR);
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__raw_writel(CONFIG_SYS_PIOC_PPUDR_VAL, AT91_BASE_PIOC + PIO_PUDR);
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#endif
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#if defined(AT91_MATRIX_EBI0CSA)
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at91_sys_write(AT91_MATRIX_EBI0CSA, CONFIG_SYS_MATRIX_EBI0CSA_VAL);
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#else /* AT91_MATRIX_EBICSA */
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at91_sys_write(AT91_MATRIX_EBICSA, CONFIG_SYS_MATRIX_EBICSA_VAL);
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#endif
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/* flash */
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at91_sys_write(AT91_SMC_MODE(CONFIG_SYS_SMC_CS), CONFIG_SYS_SMC_MODE_VAL);
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at91_sys_write(AT91_SMC_CYCLE(CONFIG_SYS_SMC_CS), CONFIG_SYS_SMC_CYCLE_VAL);
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at91_sys_write(AT91_SMC_PULSE(CONFIG_SYS_SMC_CS), CONFIG_SYS_SMC_PULSE_VAL);
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at91_sys_write(AT91_SMC_SETUP(CONFIG_SYS_SMC_CS), CONFIG_SYS_SMC_SETUP_VAL);
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/*
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* PMC Check if the PLL is already initialized
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*/
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r = at91_sys_read(AT91_PMC_MCKR);
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if (r & AT91_PMC_CSS)
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goto end;
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/*
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* Enable the Main Oscillator
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*/
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at91_sys_write(AT91_CKGR_MOR, CONFIG_SYS_MOR_VAL);
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do {
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r = at91_sys_read(AT91_PMC_SR);
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} while (!(r & AT91_PMC_MOSCS));
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/*
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* PLLAR: x MHz for PCK
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*/
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at91_sys_write(AT91_CKGR_PLLAR, CONFIG_SYS_PLLAR_VAL);
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do {
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r = at91_sys_read(AT91_PMC_SR);
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} while (!(r & AT91_PMC_LOCKA));
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/*
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* PCK/x = MCK Master Clock from SLOW
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*/
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at91_sys_write(AT91_PMC_MCKR, CONFIG_SYS_MCKR1_VAL);
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pmc_check_mckrdy();
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/*
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* PCK/x = MCK Master Clock from PLLA
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*/
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at91_sys_write(AT91_PMC_MCKR, CONFIG_SYS_MCKR2_VAL);
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pmc_check_mckrdy();
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/*
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* Init SDRAM
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*/
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/*
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* SDRAMC Check if Refresh Timer Counter is already initialized
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*/
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r = at91_sys_read(AT91_SDRAMC_TR);
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if (r)
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goto end;
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/* SDRAMC_MR : Normal Mode */
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at91_sys_write(AT91_SDRAMC_MR, AT91_SDRAMC_MODE_NORMAL);
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/* SDRAMC_TR - Refresh Timer register */
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at91_sys_write(AT91_SDRAMC_TR, CONFIG_SYS_SDRC_TR_VAL1);
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/* SDRAMC_CR - Configuration register*/
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at91_sys_write(AT91_SDRAMC_CR, CONFIG_SYS_SDRC_CR_VAL);
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/* Memory Device Type */
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at91_sys_write(AT91_SDRAMC_MDR, CONFIG_SYS_SDRC_MDR_VAL);
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/* SDRAMC_MR : Precharge All */
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at91_sys_write(AT91_SDRAMC_MR, AT91_SDRAMC_MODE_PRECHARGE);
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/* access SDRAM */
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access_sdram();
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/* SDRAMC_MR : refresh */
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at91_sys_write(AT91_SDRAMC_MR, AT91_SDRAMC_MODE_REFRESH);
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/* access SDRAM 8 times */
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for (i = 0; i < 8; i++)
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access_sdram();
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/* SDRAMC_MR : Load Mode Register */
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at91_sys_write(AT91_SDRAMC_MR, AT91_SDRAMC_MODE_LMR);
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/* access SDRAM */
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access_sdram();
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/* SDRAMC_MR : Normal Mode */
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at91_sys_write(AT91_SDRAMC_MR, AT91_SDRAMC_MODE_NORMAL);
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/* access SDRAM */
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access_sdram();
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/* SDRAMC_TR : Refresh Timer Counter */
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at91_sys_write(AT91_SDRAMC_TR, CONFIG_SYS_SDRC_TR_VAL2);
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/* access SDRAM */
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access_sdram();
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/* User reset enable*/
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at91_sys_write(AT91_RSTC_MR, CONFIG_SYS_RSTC_RMR_VAL);
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#ifdef CONFIG_SYS_MATRIX_MCFG_REMAP
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/* MATRIX_MCFG - REMAP all masters */
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at91_sys_write(AT91_MATRIX_MCFG0, 0x1FF);
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#endif
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end:
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board_init_lowlevel_return();
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}
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